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19 - 5378; rev 2 ; 10 / 13 for pricing, delivery, and ordering information, please contact maxim direct at 1- 888 - 629 - 4642, or visit maxim integrateds website at www.maximintegrated. com. 71m6545/71M6545H metrology processors general description the 71m6545/71m6545 h m etrology p rocessor s are based on 4 th - generation metering architecture supporting the 71m6xxx series of isolated current sensing products that offer drastic reduction in component count, immunity to magnetic tampering , and unparalleled reliability. the 71m6545/ 71m6545 h integrate our single converter technology? with a 22 - bit delta - sigma adc, a customizable 32 - bit computation engine (ce) for core metrology functions , as well as a user - programmable 8051 - compatible application processor (mpu) core with up to 64kb flash and up to 5kb ram. an external host pr ocessor can access metrology functions di - rectly through the spi ? interface, or alternatively through the embedded mpu core in applications requiring metrology data capture, storage , and preprocessing within the metrology subsystem. in addition, the device s integrate an rtc, dio , and uart. a complete array of ice and development tools, programming libraries , and reference designs enable rapid development and certification of meters that meet all ansi and iec electricity metering standards worldwide. mpu rtc timers xin xout rx v3p3a v3p3 sys vbat_rtc gnda gndd dio ice load dio serial port oscillator/ pll mux and adc dio, pulses, leds compute engine flash memory ram 32 khz regulator power supply 71m6545/h temperature sensor vref pwr mode control pb neutral i 2 c or wire eeprom 10/7/2010 rtc battery v3p3d battery monitor spi interface host wpulse rpulse spi_ckispi_csz spi_dispi_do xfer_busy xpulseypulse sag tx 3.3 vdc pulses 24 t m u x iadc0 vadc8 ( va ) iadc 2 vadc9 (vb) iadc 4 vadc10 (vc) c ba neutral shunt resistor sensors iadc 6 iadc1 iadc 3 iadc 5 iadc 7 resistor dividers pulse transformers a b c } in* } ia } ib } ic 71m6xx371m6xx3 71m6xx3 this system is referenced to neutral *in = optional neutral current features ? 0.1% typical accuracy ove r 2000:1 current ra nge ? exceeds iec 62053/ansi c12.20 s tandards ? seven sensor inpu ts with neutral current measurement, differential mode sel ectable for current inp uts ? selectable g ain of 1 or 8 for one current inpu t to support shun ts ? high -s peed wh/varh pulse o utputs with programmable wi dth ? flash/ram size 32kb/3kb (71m6545) 64kb/5kb (71M6545H) ? up to four pulse output s with pulse co unt ? four - quadrant metering , phase seq uencing ? digital temperature compe nsation metrology co mpensation accurate r tc for tou f unctions with automatic temperature com pensation for c rystal in all power mo des ? independent 32 - bit compute eng ine ? 46C 64 hz line frequency range with the same ca libration ? p hase c ompensation ( 7 ) ? 1 a supply current in sleep mode ? flash security ? in - system program updat e ? 8-b it mpu (80515), u p to 5 mips , for optional implementation of p ostprocessing and host support funct ions ( optional use) ? up to 29 dio pi ns ? hardware watchdog ti mer (wdt) ? i 2 c/microwire? eeprom interface ? spi in terface for h ost : full ac cess to shared memory spa ce f lash program cap ability ? uart ? industrial temperature ran ge ? 64 - pin lead (pb) - fr ee lqfp p ackage single converter technology is a registered trademark of maxim integrated products, inc. microwire is a registered trademark of national semiconductor corp. downloaded from: http:///
71m6545/71M6545H data sheet 2 v2 table of contents 1 introduction ....................................................................................................................................... 10 2 hardware description ....................................................................................................................... 11 2.1 hardware overview ................................................................................................................... 11 2.2 analog front end (afe) ............................................................................................................. 12 2.2.1 signal input pins ............................................................................................................ 13 2.2.2 input multiplexer............................................................................................................. 14 2.2.3 delay compensation ..................................................................................................... 19 2.2.4 adc pre-amplifier ......................................................................................................... 20 2.2.5 a/d converter (adc) ..................................................................................................... 20 2.2.6 fir filter ........................................................................................................................ 20 2.2.7 voltage references ....................................................................................................... 20 2.2.8 71m6xx3 isolated sensor interface ............................................................................... 21 2.3 digital computation engine (ce) ............................................................................................... 25 2.3.1 ce program memory ..................................................................................................... 25 2.3.2 ce data memory ........................................................................................................... 25 2.3.3 ce communication with the mpu ................................................................................. 25 2.3.4 meter equations ............................................................................................................. 26 2.3.5 real-time monitor (rtm) .............................................................................................. 26 2.3.6 pulse generators ........................................................................................................... 26 2.3.7 ce functional overview ................................................................................................ 28 2.4 80515 mpu core ....................................................................................................................... 30 2.4.1 mpu setup code ........................................................................................................... 30 2.4.2 80515 mpu overview .................................................................................................... 30 2.4.3 memory organization and addressing .......................................................................... 31 2.4.4 special function registers (sfrs)................................................................................ 33 2.4.5 generic 80515 special function registers ................................................................... 34 2.4.6 instruction set ................................................................................................................ 36 2.4.7 uarts ........................................................................................................................... 36 2.4.8 timers and counters ..................................................................................................... 38 2.4.9 wd timer (software watchdog timer) ......................................................................... 40 2.4.10 interrupts ........................................................................................................................ 40 2.5 on-chip resources ................................................................................................................... 46 2.5.1 physical memory............................................................................................................ 46 2.5.2 oscillator ........................................................................................................................ 48 2.5.3 pll and internal clocks ................................................................................................. 48 2.5.4 real-time clock (rtc) ................................................................................................. 49 2.5.5 71m6545/h temperature sensor .................................................................................. 53 2.5.6 71m6xx3 temperature sensor ...................................................................................... 54 2.5.7 71m6545/h battery monitor ........................................................................................... 55 2.5.8 71m6xx3 vcc monitor ................................................................................................... 55 2.5.9 uart interface .............................................................................................................. 55 2.5.10 dio pins ......................................................................................................................... 55 2.5.11 eeprom interface ........................................................................................................ 57 2.5.12 spi slave port................................................................................................................ 60 2.5.13 hardware watchdog timer ............................................................................................ 64 2.5.14 test ports (tmuxout and tmux2out pins) ............................................................. 64 downloaded from: http:///
71m6545/71M6545H data sheet v2 3 3 functional description ................................................... ................................................... ............... 66 3.1 theory of operation ................................................... ................................................... ............. 66 3.2 slp mode (sleep mode) ................................................... ................................................... ...... 66 3. 3 fault and reset behavior ................................................... ................................................... .... 68 3.3.1 events at power - down ................................................... ............................................... 68 3.3.2 reset sequence ................................................... ................................................... ...... 68 3.4 data flow and host communication ................................................... ...................................... 69 4 application information ................................................... ................................................... .............. 71 4.1 connecting 5 v devices ................................................... ................................................... ....... 71 4.2 directly connected sensors ................................................... ................................................... 71 4.3 systems using 71m6xx3 isolated sensors and current shunts ............................................... 72 4.4 system using current transformers ................................................... ...................................... 73 4.5 metrology temperature compensation ................................................... .................................. 74 4.5.1 distinction between standard and high - precision parts .............................................. 74 4.5.2 temperature coefficients for the 71m6545 ................................................... ................ 75 4.5.3 temperature coefficients for the 71M6545H ................................................... ............. 75 4.5.4 temperature coefficients for the 71m6603 and 71m6103 (1% energy accuracy) ....... 75 4.5.5 temperature compensation for vref and shunt sensors .......................................... 75 4.5.6 temperature compensation of vref and current transformers ................................ . 77 4.6 connecting i 2 c eeproms ................................................... ................................................... .. 79 4.7 connecting three - wire eeproms ................................................... ........................................ 79 4.8 uart (tx/rx) ................................................... ................................................... ..................... 79 4.9 connecting the reset pin ................................................... ................................................... .... 79 4.10 connecting the emulator port pins ................................................... ......................................... 80 4.11 flash programming ................................................... ................................................... .............. 80 4.11.1 flash programming via the ice port ................................................... .......................... 80 4.11.2 flash programming via the spi port ................................................... .......................... 80 4.12 mpu demonstration code ................................................... ................................................... ... 80 4.13 crystal oscillator ................................................... ................................................... .................. 81 4.14 meter calibration ................................................... ................................................... .................. 81 5 firmware interface ................................................... ................................................... ...................... 82 5.1 i/o ram map C functional order ................................................... ............................................ 82 5.2 i/o ram map C alphabetical order ................................................... ........................................ 88 5.3 reading the info page (71M6545H only) ................................................... ............................... 98 5.4 ce interface description ................................................... ................................................... .... 100 5.4.1 ce program ................................................... ................................................... ........... 100 5.4.2 ce data format ................................................... ................................................... ..... 100 5.4.3 constants ................................................... ................................................... ............... 100 5.4.4 environment ................................................... ................................................... ........... 101 5.4.5 ce calculations ................................................... ................................................... ..... 101 5.4.6 ce front end data (raw data) ................................................... ................................ 102 5.4.7 ce status and control ................................................... ............................................. . 103 5.4.8 ce transfer variables ................................................... ............................................. . 105 5.4.9 pulse generation ................................................... ................................................... ... 107 5.4.10 ce calibration parameters ................................................... ....................................... 110 5.4.11 ce flow diagrams ................................................... ................................................... . 111 downloaded from: http:///
71m6545/71M6545H data sheet pds_6545_009 4 v2 6 71m6545/h specifications ................................................... ................................................... ........ 113 6.1 absolute maximum ratings ................................................... .................................................. 113 6.2 recommended external components ................................................... .................................. 114 6.3 recommended operating conditions ................................................... ................................... 114 6.4 performance specifications ................................................... .................................................. 115 6.4.1 input logic levels ................................................... ................................................... .. 115 6.4.2 output logic levels ................................................... .................................................. 115 6.4.3 battery monitor ................................................... ................................................... ....... 115 6.4.4 temperature monitor ................................................... ................................................ 116 6.4.5 supply current ................................................... ................................................... ....... 117 6.4.6 v3p3d switch ................................................... ................................................... ........ 117 6.4.7 in ternal power fault comparators ................................................... ............................ 118 6.4.8 2.5 v voltage regulator C system power ................................................... ................ 118 6.4.9 crystal oscillator ................................................... ................................................... .... 118 6.4.10 phase - locked loop (pll) ................................................... ........................................ 119 6.4.11 71m6545/h vref ................................................... ................................................... .. 120 6.4.12 adc converter (71m6545/h) ................................................... ................................... 121 6.4.13 pre - amplifier for iadc0 - iadc1 ................................................... ................................ 122 6.5 timing specifications ................................................... ................................................... ......... 123 6.5.1 flash memory ................................................... ................................................... ........ 123 6.5.2 sp i slave ................................................... ................................................... ............... 123 6.5.3 eeprom interface ................................................... ................................................... 123 6.5.4 reset pin ................................................... ................................................... ............. 124 6.5.5 real -t ime clock (rtc) ................................................... ............................................ 124 6.6 64 - pin lqfp package outline drawing ................................................... ............................... 125 6.7 71m6545/h pinout ................................................... ................................................... ............. 126 6.8 71 m6545/h pin descriptions ................................................... ................................................ 127 6.8.1 71m6545/h power and ground pins ................................................... ........................ 127 6.8.2 71m6545/h analog pins ................................................... ........................................... 128 6.8.3 71m6545/h digital pins ................................................... ............................................ 129 6.8.4 i/o equivalent circuits ................................................... ............................................. . 130 7 ordering information ................................................... ................................................... ................ 131 7.1 71m6545/h ordering guide ................................................... .................................................. 131 8 related information ................................................... ................................................... ................ 131 9 contact information ................................................... ................................................... ............... 131 append ix a: acronyms ................................................... ................................................... .................... 132 appendix b: revision history ................................................... ................................................... ......... 133 downloaded from: http:///
71m6545/71M6545H data sheet v2 5 figures figure 1: ic functional block diagram ................................................... ................................................... ... 9 figure 2: afe block diagram (shunts: one - local, three - remotes) ................................................... ...... 12 figure 3. afe block diagram (four cts) ................................................... ................................................ 13 figure 4: states in a multiplexer frame ( mux_div[3:0] = 6) ................................................... .................. 17 figure 5: states in a multiplexer frame ( mux_div[3:0] = 7) ................................................... .................. 17 figure 6: general topology of a chopped amplifier ................................................... ............................... 20 figure 7: cross signal with chop_e = 00 ................................................... ............................................ 21 figure 8: rtm timing ................................................... ................................................... .......................... . 26 figure 9. pulse generator fifo timing ................................................... ................................................... 28 figure 10: samples from multiplexer cycle (frame) ................................................... ............................... 29 figure 11: accumulation interval ................................................... ................................................... .......... 29 figure 12: interrupt structure ................................................... ................................................... ................ 45 figure 13: automatic temperature compensation ................................................... .................................. 52 figure 14: connecting an external load to dio pins ................................................... .............................. 57 figure 15: 3 - wire interface. write command, hiz=0. ................................................... ............................. 59 figure 1 6: 3 - wire interface. write command, hiz=1 ................................................... .............................. 59 figure 17: 3 - wire interface. read command. ................................................... ......................................... 59 figure 18: 3 - wire interface. write command when cnt=0 ................................................... ................... 59 figure 19: 3 - wire interface. write command when hiz=1 and wfr=1. ................................................... 59 figure 20: spi slave port - typical multi - byte read and write operations ................................................ 61 figure 21: voltage, current, momentary and accumulated energy ................................................... ........ 66 figure 22: data fl ow ................................................... ................................................... ............................. 69 figure 23: resistive voltage divider (voltage sensing) ................................................... .......................... 71 figure 24. ct with single - ended input connection (current sensing) ................................................... ... 71 figure 25: ct with differential input connection (current sensing) ................................................... ....... 71 figure 26: differential resistive shunt connections (current sensing) ................................................... .. 71 figure 27: system using three - remotes and one - local (neutral) sensor .............................................. 72 figure 28. system using current transformers ................................................... ...................................... 73 figure 29: i 2 c eeprom connection ................................................... ................................................... .... 79 figure 30: connections for the uart ................................................... ................................................... ... 79 figure 31: external components for the reset pin: push - button (left), production circuit (right) ........ 80 figure 32: external components for the emulator interface ................................................... ................... 80 figure 33. trim fuse bit mapping ................................................... ................................................... ......... 98 figure 34: ce data flow: multiplexer and adc ................................................... ..................................... 111 figure 35: ce data flow: scaling, gain control, intermediate variables for o ne phase ......................... 111 figure 36: ce data flow: squaring and summation stages ................................................... ................. 112 figure 37: 64 - pin lqfp package outline ................................................... ............................................. . 125 figure 38: pinout for the lqfp - 64 package ................................................... .......................................... 126 figure 39: i/o equivalent circuits ................................................... ................................................... ....... 130 downloaded from: http:///
71m6545/71M6545H data sheet pds_6545_009 6 v2 tables table 1. required ce code and settings for 1 - local / 3 - remotes ................................................... ......... 15 table 2. required ce code and settings for ct sensors ................................................... ...................... 16 table 3: multiplexer and adc configuration bits ................................................... ................................... 19 table 4. rcmd[4:0] bits ................................................... ................................................... ....................... 22 table 6: i/o ram control bits for isolated sensor ................................................... ................................. 24 table 7: inputs selected in multiplexer cycles ................................................... ........................................ 26 table 8: ckmpu clock frequencies ................................................... ................................................... .... 31 table 9: memory map ................................................... ................................................... .......................... . 32 table 10: internal data memory map ................................................... ................................................... ... 33 table 11: special function register map ................................................... ................................................ 33 table 12: generic 80515 sfrs - location and reset values ................................................... ................. 34 table 13: psw bit functions (sfr 0xd0) ................................................... ................................................ 35 table 14: port registers (dio0 - 14) ................................................... ................................................... ...... 36 table 15: stretch memory cycle width ................................................... ................................................... 36 table 16: baud rate generation ................................................... ................................................... .......... 37 table 17: uart modes ................................................... ................................................... ......................... 37 table 18: the s0con (uart0) register (sfr 0x98) ................................................... .............................. 38 table 19: pcon register bit description ( sfr 0x87 ) ................................................... .............................. 38 table 20: timers/counters mode description ................................................... ......................................... 39 table 21: allowed timer/counter mode combinations ................................................... ........................... 39 table 22: tmod register bit description (sfr 0x89) ................................................... ............................. 39 table 23: the tcon register bit functions (sfr 0x88) ................................................... ......................... 40 table 24: the ien0 bit functions (sfr 0xa8) ................................................... ......................................... 41 table 25: the ien1 bit functions (sfr 0xb8) ................................................... ......................................... 41 table 26: the ien2 bit functions (sfr 0x9a) ................................................... ......................................... 41 table 27: tcon bit functions (sfr 0x88) ................................................... ............................................. . 41 table 28: the t2con b it functions (sfr 0xc8) ................................................... .................................... 42 table 29: the ircon bit functions (sfr 0xc0) ................................................... ..................................... 42 table 30: external mpu interrupts ................................................... ................................................... ........ 42 table 31: interrupt enable and flag bits ................................................... ................................................. 43 table 32: interrupt priority level groups ................................................... ................................................. 43 table 33: interrupt priority levels ................................................... ................................................... ......... 44 table 34: interrupt priority registers ( ip0 and ip1 ) ................................................... ................................. 44 table 35: interrupt polling sequence ................................................... ................................................... .... 44 table 36: interrupt vectors ................................................... ................................................... .................... 44 table 37: flash memory access ................................................... ................................................... ........... 46 table 38: flash security ................................................... ................................................... ....................... 47 table 39: clock system summary ................................................... ................................................... ........ 49 table 40: rtc control registers ................................................... ................................................... .......... 50 table 41: i/o ram registers for rtc temperature compensation ................................................... ....... 51 table 42: i/o ram regi sters for rtc interrupts ................................................... ..................................... 53 table 43: i/o ram registers for temperature and battery measurement ................................................ 54 table 44: data/direction registers and internal resources for dio0 to di o14 ........................................ 55 table 45: data/direction registers for dio19 - 25 and dio28 - 29 ................................................... ............ 56 table 46: data/direction registers for dio55 ................................................... ......................................... 56 table 47: selectable resources using the dio_rn[2:0] bits ................................................... .................. 56 table 48: eectrl bits for 2 - pin interface ................................................... ................................................ 57 table 49: eectrl bits for the 3 - wire interface ................................................... ........................................ 58 downloaded from: http:///
71m6545/71M6545H data sheet v2 7 table 50: spi transaction fields ................................................... ................................................... .......... 61 table 51: spi command sequences ................................................... ................................................... .... 62 table 52: spi registers ................................................... ................................................... ........................ 62 tabl e 53: tmux[4:0] selections ................................................... ................................................... ........... 64 table 54: tmux2[4:0] selections ................................................... ................................................... ......... 65 table 55: available circuit functions ................................................... ................................................... .... 67 table 56: vstat[2:0] (sfr 0xf9[2:0]) ................................................... ................................................... .. 68 table 57: gain_adjn compensation channels (figure 2, figure 27, table 1) ........................................ 76 table 58: gain_adjx compensation channels (figure 3, figure 28, table 2) ........................................ 78 table 59: i/o ram map C functional order, basic configuration ................................................... ........... 82 table 60: i/o ram map C functional order ................................................... ............................................ 84 table 61: i/o ram map C alphabetical order ................................................... ......................................... 88 table 62. info page trim fuses ................................................... ................................................... ............ 98 table 63: ce equ[2:0] equations and element input mapping ................................................... ............ 101 table 64: ce raw data access locations ................................................... ............................................ 102 table 65: cestatus register ................................................... ................................................... ............. 103 table 66: cestatus bit definitions ................................................... ................................................... .... 103 table 67: ceconfig register ................................................... ................................................... ............ 103 table 68: ceconfig bit definitions (ce ram 0x20) ................................................... ............................ 104 table 69: sag threshold, phase measurement, and gain adjust control ............................................... 105 table 70: ce transfer variables (with shunts) ................................................... ...................................... 105 table 71: ce transfer variables (with cts) ................................................... .......................................... 106 table 72: ce energy measurement variables (with shunts) ................................................... ................ 106 table 73: ce energy measurement variables (with cts) ................................................... ..................... 106 table 74: other transfer variables ................................................... ................................................... ..... 107 table 75: ce pulse generation parameters ................................................... .......................................... 108 table 76: ce parameters for noise suppression and code version ................................................... .... 109 table 77: ce calibration parameters ................................................... ................................................... . 110 table 78: absolute maximum ratings ................................................... ................................................... 113 table 79: recommended external components ................................................... ................................... 114 table 80: recommended operating conditions ................................................... .................................... 1 14 table 81: input logic levels ................................................... ................................................... ............... 115 table 82: output logic levels ................................................... ................................................... ............ 115 table 83: battery monitor performance specifications ( temp_bat = 1) ................................................. 115 table 84. temperature monitor ................................................... ................................................... .......... 116 table 85: supply current performance specifications ................................................... .......................... 117 table 86: v3p3d switch performance specifications ................................................... ........................... 117 table 87: 2.5 v voltage regulator performance specifications (vdd pin) .............................................. 118 table 88: crystal oscillator performance specifications ................................................... ....................... 118 table 89: pll performance specifications ................................................... ............................................ 119 table 90: 71m6545/h vref performance specifications ................................................... ..................... 120 table 91: adc converter performance specifications ................................................... .......................... 121 ta ble 92: pre - amplifier performance specifications ................................................... ............................. 122 table 93: flash memory timing specifications ................................................... ..................................... 123 table 94. spi slave timing specifications ................................................... ............................................ 123 table 95: eeprom interface timing ................................................... ................................................... .. 123 table 96: reset pin timing ................................................... ................................................... .............. 124 table 97: rtc range for date ................................................... ................................................... ........... 124 table 98: 71m6545/h power and ground pins ................................................... ..................................... 127 table 99: 71m6545/h analog pins ................................................... ................................................... ..... 128 downloaded from: http:///
71m6545/71M6545H data sheet pds_6545_009 8 v2 table 100: 71m6545/h digital pins ................................................... ................................................... .... 129 table 101. 71m6545/h ordering guide ................................................... ................................................. 131 downloaded from: http:///
71m6545/71M6545H data sheet v2 9 test iadc0 mux and preamp xin xout vref ckadc ce 32-bit compute engine mpu (80515) ce control reset vbias emulator port 3 ce_busy uart tx rx xfer busy cedata 0x000...0x2ff prog 0x000...0x3ff data 0x0000...0xffff program 0x0000...0xffff 0x0000 0xffff digital i/o configuration ram (i/o ram) 0x2000...0x20ff i/o ram memory share 0x0000...0x13ff 16 8 rtclk rtclk (32khz) mux_sync ckce ckmpu ck32 32 8 8 8 power fault detection 4.9 mhz < 4.9mhz 4.9 mhz gndd v3p3a v3p3d voltage regulator 2.5v to logic vdd 32khz mpu_rstz faultz wake con- figuration parameters gnda vbias april 2011 cross clock gen oscillator 32 khz ck32 mck pll vref div adc mux ctrl strt mux mux ckfir rtm dio pins wpulse varpulse wpulse varpulse test mode < 4.9mhz ckmpu_2x ckmpu_2x sdck sdout sdin e_rxtx e_tclk e_rst flash 64 kb v3p3a fir eeprom interface ck_4x pb rtc vbias memory share 16 e_rxtx e_tclk e_rst(open drain) ice_e ? ad converter + - vref v3p3sys test mux mpu ram (5 kb) 22 spi vstat vbat_rtc iadc1iadc2 iadc3 iadc4 iadc5 iadc6 iadc7 vadc8vadc9 vadc10 test mux 2 non-volatile configuration ram bat test temp sensor rtm tmuxout tmu2xout gnda gndd spi i/f figure 1 : ic functional block diagram downloaded from: http:///
71m6545/71M6545H data sheet 10 v2 1 introduction this data sheet covers the 71m6545 and 71M6545H fourth generation p oly-phase metrology processors. the term ?71m6545/h? is used when discussing a device feature or behavior that is applicable to both part numbers. the appropriate part number is indicated when a de vice feature or behavior is being discussed that applies only to a specific part number. this data s heet also covers details about the companion 71m6xx3 isolated current sensor device. this document covers the use of the 71m6545/h in conjunction w ith the 71m6xx3 isolated current sensor. the 71m6545/h and 71m6xx3 ics make it possible to use one non-iso lated and three additional isolated shunt current sensors to create poly-phase energy meters usin g inexpensive shunt resistors, while achieving unprecedented performance with this type of senso r technology. the 71m6545/h metrology processors also support current transformers (ct). to facilitate document navigation, hyperlinks are often used to reference figures, tables and section headings that are located in other parts of the document. all hype rlinks in this document are highlighted in blue . hyperlinks are used extensively to increase the level of detail and clarity provided within each section by referencing other relevant parts of the document. to further facilitate document navigation, this document is published as a pdf document with bookmarks enable d. the reader is also encouraged to obtain and review the docum ents listed in 8 related information on page 131 of this document. downloaded from: http:///
71m6545/71M6545H data sheet v2 11 2 hardware description 2.1 hardware overview the 71m6545/h single - chip metrology processor integrate s all primary functional blocks required to implement a solid - state electricity meter. included on the chip are : ? an a nalog front end (afe) featuring a 22 - bit second - order sigma - delta adc ? an i ndependent 32 - bit digital computation engine (ce) to implement dsp functions ? an 8051 - compatible microprocessor (mpu) which executes one inst ruction per clock cycle (80515) ? a precision voltage reference (vref) ? a temperature sensor for digital temperature compensation : - metrology digital temperature compensation (mpu) - automatic rtc digital temperature compensation operational in sleep mode (slp) ? ram and flash memory ? a real time clock (rtc) ? a variety of i/o pi ns ? a power failure interrupt (ce code feature) ? a zero - crossing interrupt (ce code feature) ? selectable current sensor interfaces for locally - connect ed sensors as well as isolated sensors ( i.e., using the 71m6xx3 companion ic with a shunt resistor sensor ) ? resistive shunt and cur rent transformers are supported in order to implement a poly - phase meter with or without neutral current sensing, one resistive shunt cur rent sensor may be connected directly (non - isolated) to the 71m6545/h device, while three additional current shunts are isolated using a companion 71m6xx3 isolated sensor ic. an inexpensive, small size pulse transformer is used to electr ically isolate the 71m6xx3 remote sensor from the 71m6545/h . the 71m6545/h performs digital communications bi - directionally with the 71m6xx3 and also provides power to the 71m6xx3 through the isolating pulse transformer. isolated (remote) shunt cu rrent sen sors are connected to the differential input of the 71m6xx3. the 71m6545/h may also be used with current transformers; in this case the 71m6xx3 isolated sensors are not required. included on the 71m6xx3 companion isolator chip are: ? digital isolation communications interface ? an a nalog front end (afe) featuring a 22 - bit second - order sigma - delta adc ? a precision voltage reference (vref) ? a temperature sensor (for current - sensing digital temperature compensation) ? a fully differential shunt resistor sensor input ? a pre - amplifier to optimize shunt current sensor performance ? isolated power circuitry obtains dc power from pulses sent by the 71m6545/h in a typical application, the 32 - bit compute engine (ce) of t he 71m6545/h sequentially processes the samples from the voltage inputs on analog input pins and performs calculations to measur e active ener gy (wh) and reactive energy (varh), as well as a 2 h, and v 2 h for four - quadrant metering. these measurements are then accessed by the host processor via the spi or by the on - chip mpu, to be processed further and output using either the peripheral devices available to the on - chip mpu or by the host processor. in addition to advanced measurement functions, the re al time clock (rtc) function allows the 71m6545/h to record time of use (tou) metering information for multi - rate applications and to time - stamp tamper or other events. a n automatic rtc temperature compensation circuit operates in all power states i ncluding when the mpu is halted, and continues to compensate using back - up battery power during power outages (vbat_rtc pin) . in addition to the temperature - trimmed ultra - precision voltage reference, the on - chip digital temperature com pensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on metrology and rtc accuracy (i.e., to meet the requirements of ansi and iec standards ) . temperature - dependent external com ponents such as the crystal , current transformers (cts) , current shunts and their corresponding signal conditioning circuits can be characterized and their downloaded from: http:///
71m6545/71M6545H data sheet pds_6545_009 12 v2 correction factors can be programmed to produce electricity meters with excepti onal accuracy over the indus trial temperature range. one of the two internal uarts is adapted to support an infrared led with internal drive and sense confi guration and can also function as a standard uart. this flexibility makes it possible to implement amr meters with an ir interface. a block diagram of the ic is shown in figure 1 . 2.2 analog front end (afe) the afe functions as a data acquisition system, controlled by the mpu or by the host processor over the spi interface . the 71m6545/h afe may also be augmented by isolated 71m6xx3 sensors in order to support low - cost current shunt sensors. figure 2 and figure 3 show two of the most common configurations; other configurations are possible. sensors that are connected directly to the 71m6545/h (i.e., ia dc0 - ia dc1 , va dc8 , v adc9 and v adc10 ) are multiplexed in to the single second - order sigma - delta adc input for sampling in the 71m6545/h . the 71m6545/h adc output is decimated by the fir filter and stored in ce ram where it can be accessed and processed by the ce . shunt current sensors that are isolated by using a 71m6xx3 device, are sampled by a second - order sigma delta adc in the 71m6xx3 and the signal samples are transferred over the digital isolation inter face through the low - cost isolation pulse transformer. figure 2 show s the 71m6545/h us ing shunt current sensors and the 71m6xx3 isolated sensor device s . figure 2 supports neutral current measurement with a local shunt connected to the ia dc0 - iadc1 input plus three remote (isolated) shunt sensors. as seen in figure 2 , when a remote isolated shunt sensor is connected via the 71m6x x3 , the samples associated with this current channel are not routed to the multiplexer, and are instead transferred digitally to the 71m6545/h via the isolation interface and are directly stored in ce ram. the mux_se ln [3:0] i/o ram control fields allow the mpu to configure the afe for the desired multiplexer sampling sequence. refer to table 1 and table 2 for the appropriate ce code and the corresponding afe settings. see figure 27 for the meter wiring configuration corresponding to figure 2 . ? adc converter vref mux vref vref vadc 22 fir iadc 2 vadc9 (vb) iadc0 vadc8 (va) iadc1 iadc 3 71m6545/h ce ram 71m6xx3 sp sn inp inn remote shunt ib digital isolation interface local shunt in* 22 iadc 4 iadc 5 71m6xx3 sp sn inp inn remote shunt ic vadc10 (vc) 22 iadc 6 iadc 7 71m6xx3 sp sn inp inn remote shunt ia 22 *in = neutral current 10/7/2010 figure 2 : afe block diagram (shunts: one - local, three - remotes) downloaded from: http:///
71m6545/71M6545H data sheet v2 13 the 71m6545/h afe can also be directly interfaced to current transformers (cts), a s seen in figure 3 . in this case, all voltage and current channels are multiplexed into a single sec ond - order sigma - delta adc in the 71m6545/h and the 71m6xx3 remote isolated sensors are not used. the fourth ct and the measureme nt of neutral current via the iadc0 - iadc1 current channel are optional. see figure 28 for the meter wiring configuration corresponding to figure 3 . ? adc converter vref mux vref vref vadc 22 fir iadc 4 vadc9 (vb) iadc2 vadc8 (va) iadc3 iadc 5 71m6545/h ce ram ib ct ia ct iadc 6 iadc 7 ic ct iadc 0 iadc 1 in* ct vadc10 (vc) 10/7/2010 *in = neutral current figure 3 . afe block diagram (four cts) 2.2.1 signal input pins the 71m6545/h features eleven adc input pins. iadc0 through iadc7 are intended for use as current sensor inputs. these eight curr ent sensor inputs can be configured as four single - ended inputs, or can be paired to form four differential inputs. for best performance, it is recommended to configure the current sensor inputs as differ ential inputs (i.e., iadc0 - iadc1, iadc2 - iadc3, iadc4 - iadc5 and iadc6 - iadc7). the first differential input (iadc0 - iadc1) features a pre - amplifier with a selectable gain of 1 or 8, and is intended for direct connect ion to a shunt resistor sensor, and can also be used with a current transformer (ct). the three remaining differential pairs (i.e., iadc2 - iadc3, iadc4 - iadc5 and iadc6 - iadc7) may be used with cts, or may be enabled to int erface to a remote 71m6x x 3 isolated current sensor providing isolation for a shunt resistor sensor using a low cost pulse transformer. the remaining three inputs vadc 8 (va), vadc 9 (vb) and vadc10 (vc) are single - ended, and are intended for sensing each of the phase voltages in a poly - phase meter application. these three single - ended inputs are referenced to the v3p3a pin. all adc input pins measure voltage. in the case of shunt current sensors, currents are sensed as a voltage drop in the shunt resistor sensor. in the case of current transformers (c t), the current is measured as a voltage across a burden resistor that is connected to the secondary of the ct. meanwhi le, line voltages are sensed through resistive voltage dividers. the vadc8 (va) , vadc9 (vb) and vadc10 (vc) pins are single - ended and their common return is the v3p3a pin. see figure 23 , figure 24 , figure 25 and figure 26 for detailed connections for each type of sensor. pins iadc0 - iadc1 can be programmed individually to be differential or single - ended as determined by the diff0 _e ( i/o ram 0 x210c[4] ) control bit. however, for most applications, iadc0 - iadc1 are downloaded from: http:///
71m6545/71M6545H data sheet pds_6545_009 14 v2 configured as a differential input to work with a resistive shunt or ct directly interfaced to the iadc0 - iadc1 differential input with the appropriate external signal conditioning components. the performance of the iadc0 - iadc1 pins can be enhanced by enabling a pre - amplifier with a fixed gain of 8, using the i/o ram control bit pre_e (i/o ram 0x2704[5]) . when pre_e = 1, iadc0 - iadc1 become the inputs to the 8x pre - amplifier, and the output of this amplifier is supplied to the multiplexer. the 8x amplification is useful when current sensors with low sensitivity, s uch as shunt resistors, are used. with pre_e set, the iadc0 - iadc1 input signal amplitude is restricted to 31.25 mv peak. when pre_e = 0 (gain = 1), the iadc0 - iadc1 input signal is restricted to 250 mv peak. for the 71m6545/h application utilizing shunt resistor sensors ( figure 2 ), the iadc0 - iadc1 pins are configured for differential mode to interface to a local shunt by setting the diff0 _e control bit. meanwhile, the iadc2 - iadc3 , iadc4 - iadc5 and iadc6 - iadc7 pins are re - configured as digital remote sensor interface designed to communicate wi th a 71m6xx3 i solated s ensor by setting the rmt x _e control bits ( i/o ram 0x2709[ 5: 3] ). the 71m6x x3 communicate s with the 71m6545/h using a bi - directional digital data stream through an isolating low - cost pulse transformer. the 71m6545/h also supplies power to the 71m6x x3 through the isolating transformer. this type of interface is further described at the end of this chapter . s ee 2.2.8 71m6xx3 isolated sensor interface . for use with current transformers (cts), as shown in figure 3 , the rmtx_e control bits are reset, so that iadc2 - iadc3, iadc4 - iadc5 and iadc6 - iadc7 are configured as local analog inputs. the iadc0 - iadc1 pins cannot be configured as a remote sensor interface. 2.2.2 input multiplexer when operating with locally connected sensors, t he input multiplexer sequentially applies the input signals from the analog input pins to the input of the adc (see figure 3 ) , according to the sampling sequence determined by the eleven muxn_sel[3:0] control fields . one complete sampling sequence is called a multiplexer frame. the multiplexer of the 71m6545/h can select up to eleven input signal s when the current sensor input s are configured for single - ended mode. when the current sensor inputs are configured in differential mode (recommended for best performance), the number of input signals is seven (i.e., ia dc0 - ia dc1 , i adc2 -i adc3 , i adc4 -i adc5 , i adc6 -i adc7 , va dc8 , v adc9 and v adc10 ) per multiplexer frame . the number of slots in the multiplexer frame is controlled by the i/o ram control fi eld mux_div [3:0] (i/o ram 0x2100[7:4]) (see figure 4 ) . the multiplexer always starts at state 0 and proceeds until the number of sensor channels determined by the mux_div [3:0] field setting have been converted. the 71m6545/h requires a unique ce code that is written for the specific meter configuration . moreover, each ce code requires specific afe and mux settings in order to function properly. table 1 provides the ce code and settings corresponding to the 1- local / 3 - remote sensor configuration shown in figure 2 . table 2 provides the ce code and settings corresponding to the ct configuration shown in fig ure 3 . downloaded from: http:///
71m6545/71M6545H data sheet v2 15 table 1 . required ce code and settings for 1 - local / 3 - remotes i/o ram mnemonic i/o ram location i/o ram setting comments fir_len[1:0] 210c[2:1] 1 288 cycles adc_div 2200[5] 0 fast pll_fast 2200[4] 1 19.66 mhz mux_div[3:0] 2100[7:4] 6 see note 1 mux0_sel[3:0] 2105[3:0] 0 slot 0 is iadc 0 - iadc1 ( in ) mux1_sel[3:0] 2105[7:4] 1 unused (see note 2) mux2_sel[3:0] 2104[3:0] 1 unused (see note 2) mux3_sel[3:0] 2104[7:4] 8 slot 3 is vadc 8 (v a) mux4_sel[3:0] 2103[3:0] 9 slot 4 is vadc 9 (vb ) mux5_sel[3:0] 2103[7:4] a slot 5 is vadc 10 (vc) mux6_sel[3:0] 2102[3:0] 0 slots not enabled mux7_sel[3:0] 2102[7:4] 0 mux8_sel[3:0] 2101[3:0] 0 mux9_sel[3:0] 2101[7:4] 0 mux10_sel[3:0] 2100[3:0] 0 rmt 2 _e 2709[3] 1 enable remote i adc2 -i adc3 (i a) rmt4 _e 2709[4] 1 enable remote iadc4 -i adc5 (i b) rmt6 _e 2709[5] 1 enable remote i adc6 -i adc7 (ic) diff0 _e 210c[4] 1 differential iadc0 - iadc1 (in) diff2 _e 210c[5] 0 see note 3 diff4 _e 210c[6] 0 see note 3 diff6 _e 210c[7] 0 see note 3 pre_e 2704[5] 1 ia dc0 - ia dc1 gain = 8 equ[2:0] 2106[7:5] 5 ia*va + ib*vb + ic*vc ce code s (see note 4) ce43b016603 (use with 71m6603) ce43b016103 (use with 71m6103) ce43b016113 (use with 71m6113) ce43b016203 (use with 71m6203) equation(s) 5 current sensor type 1 local shunt and 3 remote shunts applicable figure s figure 2 and figure 27 notes: 1. mux_div[3:0] must be set to 0 while writing the other ram locations in this table . 2. each unused slot must be assigned to a valid (0 to a), but unused adc handle . 3. this channel is remote (71m6xx3), hence diffx_e is irrelevant . 4. must u se the ce code that corresponds to the specific 71m6xx3 device used . maxim updates the ce code periodically. c ontact your local maxim representative to obtain the latest ce code and the associated settings. downloaded from: http:///
71m6545/71M6545H data sheet pds_6545_009 16 v2 table 2 . required ce code and settings for ct sensors i/o ram mnemonic i/o ram location i/o ram setting (hex) comments fir_len[1:0] 210c[2:1] 1 288 cycles adc_div 2200[5] 0 fast pll_fast 2200[4] 1 19.66 mhz mux_div[3:0] 2100[7:4] 7 see note 1 mux0_sel[3:0] 2105[3:0] 2 slot 0 is iadc 2 - iadc3 (i a) mux1_sel[3:0] 2105[7:4] 8 slot 1 is vadc 8 (v a) mux2_sel[3:0] 2104[3:0] 4 slot 2 is iadc 4 - iadc5 (ib ) mux3_sel[3:0] 2104[7:4] 9 slot 3 is vadc 9 (v b) mux4_sel[3:0] 2103[3:0] 6 slot 4 is iadc 6 - iadc7 (ic ) mux5_sel[3:0] 2103[7:4] a slot 5 is vadc 10 (v c) mux6_sel[3:0] 2102[3:0] 0 slot 6 is iadc0 - iadc1 ( in C see note 2 ) mux7_sel[3:0] 2102[7:4] 0 slots not enabled mux8_sel[3:0] 2101[3:0] 0 mux9_sel[3:0] 2101[7:4] 0 mux10_sel[3:0] 2100[3:0] 0 rmt2 _e 2709[3] 0 local sensor iadc2 - iadc3 rmt4 _e 2709[4] 0 local sensor iadc4 - iadc5 rmt6 _e 2709[5] 0 local sensor iadc6 - iadc7 diff0 _e 210c[4] 1 differential iadc0 - iadc1 diff2 _e 210c[5] 1 differential iadc2 - iadc3 diff4 _e 210c[6] 1 differential iadc4 - iadc5 diff6 _e 210c[7] 1 differential iadc6 - iadc7 pre_e 2704[5] 0 ia dc0 - iadc1 gain = 1 equ[2:0] 2106[7:5] 5 ia*va + ib*vb + ic*vc ce code ce43a02 equation(s) 5 current sensor type 4 current transformers (cts) applicable figure s figure 3 and figure 28 notes: 1. mux_div[3:0] must be set to 0 while writing the other ram locations in this table . 2. in is the optional neutral current . maxim updates the ce code periodically. c ontact your local maxim representative to obtain the latest ce code and the associated settings. using settings for the i/o ram mnemonics listed in table 1 a nd table 2 that do not match those required by the corresponding ce code being used may result in undesirable side effects and must not be selected by the mpu. consult your local maxim represen tative to obtain the correct ce code and afe / mux settings corresponding to the application. for a poly - phase configuration with neutral current sensing using shunt resistor current sensors and the 71m6xx3 isolated sensors, as shown in figure 2 , the iadc0 - iadc1 input must be configured as a differential input, to be connected to a local shunt (see figure 26 for the shunt connection details). the local shunt connected to the ia dc0 - iadc1 input is used to sense the n eutral current. the voltage sensors (va dc8 , v adc9 and v adc10 ) are also directly connected to the 71m6545/h (see figure 23 for the connection details) and are also routed though the multiplexer, as seen in figure 2 . meanwhile, the downloaded from: http:///
71m6545/71M6545H data sheet v2 17 iadc2 - iadc3, i adc4 - iadc5 and i adc6 - iadc7 current inputs are configured as remote sensor digital inter faces and the corresponding samples are not routed through the multiplexer. for t his configuration, the multiplexer sequence is as shown in figure 4 . for a poly - phase configuration with optional neutral current sensing using current transformer (cts) sensors, as shown in figure 3 , all four current sensor inputs must be configured as a differential input s , to be connected to their corresponding cts (see figure 25 for the differential ct connection details). the i adc0 - iadc1 current sensor input is optionally used to sense the neutral current for ant i - tampering purposes . the voltage sensors (va dc8 , v adc9 and v adc10 ) are directly connected to the 71m6545/h (see figure 23 for the voltage sensor connection details). no 71m6xx3 isolated sensors are used in this configuration and all sensors are routed th r ough the multiplexer, as seen in figure 3 . for this configuration, the multiplexer sequence is as shown in figure 5 . the multiplexer sequence shown in figure 4 , covers the shunt configuration shown in figure 2 . t he frame duration is 13 ck32 cycles (where ck32 = 32 , 768 hz), therefore, the resulting sample rate is 32 , 768 hz / 13 = 2 , 520.6 hz. no te that figure 4 only shows the currents that pass through the 71m6545/h multiplexer, and does not show the currents that are copied directly into ce ram from the remote sensors (see figure 2 ), which are sampled during the second half of the multiplexer frame. the two unused conversio n slots shown are necessary to produc e the desired 2,520.6 hz sample rate. ck32 mux state 0 1 2 3 4 5 mux_div[3:0] = 6 conversions settle multiplexer frame s cross mux_sync s in unused unused va vb vc 1 local / 3 remotes: figure 4 : states in a multiplexer frame ( mux_div [3:0] = 6) the multiplexer sequence shown in figure 5 corresponds to the ct configuration shown in figure 3 . since in this case all current sensors are locally connected to the 71m6545/h , all currents are routed through the multiplexer, as seen in figure 3 . for this multiplexer sequence, the frame duration is 15 ck32 cycles (where ck32 = 32,768 hz), therefore, the resulting sample rate is 32,768 hz / 15 = 2,184.5 hz. ck32 mux state 0 1 2 3 4 5 mux_div[3:0] = 7 conversions settle multiplexer frame s cross mux_sync s 6 ia va ib vb ic vc in figure 5 : states in a multiplexer frame ( mux_div [3:0] = 7) mult iplexer advance, fir initiation and chopping of the adc reference voltage (using the internal cross signal, see 2.2.7 voltage references ) are controlled by the internal mux_ctrl c ircuit . additionally, mux_ctrl launches each pass of the ce through its code. conceptually, mux_ctrl is clocked by ck32, the 32768 hz clock from the pll block. the behavior of the mux_ctrl circuit is governed by : ? chop_e[1:0] ( i/o ram 0x2106[3:2] ) ? mux_ div[3:0] ( i/o ram 0x2100[7:4] ) downloaded from: http:///
71m6545/71M6545H data sheet pds_6545_009 18 v2 ? fir_len [1:0] ( i/o ram 0x210c[2:1 ] ) ? adc_div ( i/o ram 0x2200[5] ) the duration of each multiplexer state depends on the number of adc samples processed by the fir as determined by the fir_len [1:0] (i/o ram 0x210c[2:1] control field . each multiplexer state start s on the rising edge of ck32, the 32 - khz clock. it is required that mux_div [3:0] (i/o ram 0x2100 [7:4 ]) be set to zero while changing the adc configuration t o minimize system transients . after all configuration bits are set, mux_div [3:0] should be set to the required value. the duration of each time slot in ck32 cycles depends on fir_len [1:0], adc_div and pll_fast : time_slot_duration ( pll_fast = 1) = ( fir_len [1:0] +1 ) * ( adc_div +1) time_slot_duration ( pll_fast = 0) = 3* ( fir_len [1:0] +1 ) * ( adc_div +1) th e duration of a multiplexer frame in ck32 cycles is: mux_f rame _d uration = 3- 2* pll_fast + time_slot_duration * mux_div [3:0] the duration of a multiplexer frame i n ck_fir cycles is: mux frame duration (ck_fir cycles) = [3 - 2* pll_fast + time_slot_duration * mux_div ] * (48+ pll_fast *102) the adc conversion sequence is programmable through the mux n _sel control fields ( i/o ram 0x2100 to 0x2105 ). as stated above, there are up to eleven adc time slots in the 71m6545/h , as set by mux_div[3:0] ( i/o ram 0x210 0[7:4] ) . in the expression mux n _sel [3:0] = x , n refers to the multiplexer frame time slot number and x refers to the desired adc input number or adc handle (i.e., iadc0 to vadc10 , or simply 0 to 10 decimal). thus, there are a total of 11 valid adc ha ndles in th e 71m6545/h devices. for example, if mux 0 _sel [3:0] = 0 , then iadc0 , corresponding to the sample from the iadc0 - iadc1 input (configured as a differential input), is positioned in the multiplexer frame during time slot 0 . see table 1 and table 2 for the appro priate mux n _sel[3:0] settings and other settings applicable to a particular meter configuration and ce code. note that when the remote sensor interface is enabled, the samples corresponding to the remote sensor current s do not pass through the 71m6545/h mu ltiplexer. the sampling of the remote current sensors occurs in the second half of the multiplexer frame. the va, vb and vc voltages are assigned the last three slots in the frame. with this slot assignment for va, vb and vc, t he sampling of the corresponding remote sensor current s bears a precise timing relationship to their corresponding phase voltages, and delay compensation is accurately performed (see 2.2.3 delay compensation on page 19 ). also when using remote sensors, it is necessary to introduce un used slots to realize the number of slots specifi ed by the mux_div[3:0] ( i/o ram 0x2100[7:4] ) field setting (see figure 4 and figure 5 ). t he mux n _sel[3:0] control fields for the se unused (dummy) slots must be written with a valid adc handle (i.e., 0 to 10 decimal) that is not otherwise being used. in this manner, the unused adc han dle , is used as a dummy place holder in the multiplexer frame, and the correct duration multiplexer frame sequence is generated and also the desired sample rate. the resulting sample data stored in the ce ram location corresponding to the dummy adc handle is ignored by the ce code. meanwhile, the digital isolation interface takes care of automatically storing the sam ples for the remote current sensors in the appropriate ce ram locations. delay compensation and other functions in the ce code require the settings for m ux_d iv[3:0], m ux n _sel [3:0], rmt_e, fir_len[1:0], adc_div and pll_fast to be fixed for a given ce code. refer to table 1 and table 2 for the settings that are applicable to the 71m6545/h . table 3 summarizes the i/o ram registers used for configuring the multiplexer, signals pins, and adc. all listed registers are 0 after reset and wake from slp mode, and are readable and writabl e. downloaded from: http:///
71m6545/71M6545H data sheet v2 19 table 3: multiplexer and adc configuration bits name location description mux0_sel[3:0] 2105[3:0] selects the adc input converted during time slot 0. mux1_sel[3:0] 2105[7:4] selects the adc input converted during time slot 1. mux2_sel[3:0] 2104[3:0] selects the adc input converted during time slot 2. mux3_sel[3:0] 2104[7:4] selects the adc input converted during time slot 3. mux4_sel[3:0] 2103[3:0] selects the adc input converted during time slot 4. mux5_sel[3:0] 2103[7:4] selects the adc input converted during time slot 5. mux6_sel[3:0] 2102[3:0] selects the adc input converted during time slot 6. mux7_sel[3:0] 2102[7:0] selects the adc input converted during time slot 7. mux8_sel[3:0] 2101[3:0] selects the adc input converted during time slot 8. mux9_sel[3:0] 2101[7:0] selects the adc input converted during time slot 9. mux10_sel[3:0] 2100[3:0] selects the adc input converted during time slot 10. adc_div 2200[5] controls the rate of the adc and fir clocks. mux_div[3:0] 2100[7:4] the number of adc time slots in each multiplexer frame (maximum = 11). pll_fast 2200[4] controls the speed of the pll and mck. fir_len[1:0] 210c[2:1] determines the number of adc cycles in the adc decimation fir filter. diff0 _e 210c[4] enables the differential configuration for analog input pins iadc0 - iadc1 . diff2 _e 210c[5] enables the differential configuration for analog input pins iadc2 - iadc3 . diff4 _e 210c[6] enables the differential configuration for analog input pins iadc4 - iadc5 . diff6 _e 210c[7] enables the differential configuration for analog input pins iadc6 - iadc7 . rmt2 _e 2709[3] enables the remote sensor interface transforming pins iadc2 - iadc3 into a digital interface for communications with a 71m6x x3 sensor. rmt4 _e 2709[4] enables the remote sensor interface transforming pins iadc4 - iadc5 into a digital interface for communications with a 71m6xx3 sensor. rmt6 _e 2709[5] enables the remote sensor interface transforming pins iadc6 - iadc7 into a digital interface for communications with a 71m6xx3 sensor. pre_e 2704[5] enables the 8x pre - amplifier. refer to table 61 starting on page 88 for more complete details about these i/o ram locations. 2.2.3 delay compensation when measuring the energy of a phase (i.e., wh and varh) in a service, the vo ltage and current for that phase must be sampled at the same instant. otherwise, the phase difference, , introduces errors. o delay o delay f t t t 360 360 ? ? = ? = where f is the frequency of the input signal , t = 1/f and t delay is the sampling delay between current and voltage . tradition ally, sampling is accomplished by using two a/d converters per phase (one f or voltage and the other one for current) controlled to sample simultaneously. max im s single - converter technology , however, exploits the 32 - bit signal processing capability of its ce to implement constant delay al l - pass filters. the all - pass filter corrects for the conversion time difference between the v oltage and the corr esponding current samples that are obtained with a single multiplexed a/d convert er. the constant delay all - pass filter provides a broad - band delay 360 o - , that is precisely matched to the differ ence in sample time between the voltage and the current of a given phase. this digita l filter does not affect the amplitude of the signal, but provides a precisely controlled phase response. the recommended adc multiplexer sequence samples the current first, immediatel y followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle relative to the current. the delay compensation implemented in the ce aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., 360 o ), then routing the voltage samples through the all - pass filter, thus delaying the voltage samples by 360 o - , resulting in the residual phase error between the current and its corresponding voltage of C . downloaded from: http:///
71m6545/71M6545H data sheet pds_6545_009 20 v2 the residual phase error is negligible, and is typically less than 1.5 milli - degrees at 100hz, thus it does not contribute to errors in the energy measurements. when using remote sensors, the ce performs the same delay compensation described above to align each voltage sam ple with its corresponding current sample. even though the remote current samples do not pass through the 71m6545/h multiplexer, their timing relationship to their corresponding voltages is fixed and precisely known, provided that the muxn_sel[3:0] slot as signment fields are programmed as shown in table 1 . note that these slot assignments result in va, vb and vc occupying multipl exer slots 3, 4 and 5, respectively (see figure 4 ). 2.2.4 adc pre -a mp lifier the adc pre - amp lifier is a low - noise differential amplifier with a fixed gain of 8 available only on the iadc0 - iadc1 sensor input pins . a gain of 8 is enabled by setting pre_e = 1 ( i/o ram 0x2704[5] ) . when disabled, the supply current of the pre - amplifier is <10 na and the gain is unity . with proper settings of the pre_e and diff0 _e ( i/o ram 0x210c[4] ) bits, the pre - amplifier can be used whether diffe rential mode is selected or not. fo r best performance, the differential mode is recommended. in order to save power, the bias current of the pre - amplifier and adc is adjusted according to the adc_div control bit ( i/o ram 0x2 200 [5] ). 2.2.5 a/d converter (adc) a single 2 nd order sigma - delta a/d converter digitizes the voltage and current inputs to the device. the resolution of the adc, including the sign bit , is 21 bits ( fir_len [1:0] = 01 , i/o ram 0x210c[ 2: 1] ), or 22 bits ( fir_len [1:0] = 10 ). the adc is clocked by ckadc. initiation of each adc conversion is controlled by the internal mux_ctrl circuit as described earlier . at the end of each adc conversion, the fir filter output data is stored into the c e ram location determined by the multiplexer selection . 2.2.6 fir filter the finite impulse response filter is an integral part of the adc and it is optimized for use with the multi plexer. the purpose of the fir filter is to decimate the adc output to the desired re solution. at the end of each adc conversion, the output data is stored into the fixed ce ram location determined by the multiplexer selection stored in the muxn_sel[3:0] fields . fir data is stored lsb - justified, but shifted left by 9 bits. 2.2.7 voltage references a bandgap circuit provides the reference voltage to the adc. the amplifier within the reference is chopper stabilized, i.e. , the chopper circuit can be enabled or disabled by the mpu using the i/o ram control field chop_e [1:0] (i/o ram 0x2106[3:2]) . the two bits in the chop_e [1:0] field enable the mpu to operate the chopper circuit in regula r or inverted operation, or in toggling mode s (recommended) . when the chopper circuit is toggled in between mul tiplexer cycles, dc offsets on vref are automatically averaged out, therefore the chopper circuit should always be configured for one of the toggling modes. since the vref band - gap amplifier is chopper - stabilized, the dc offset voltage, which is the most significant long - term drift mechanism in the voltage references (vref), is automatically removed by the chopper circuit. both the 71m6545/h and the 71m6xx3 feature chopper circuits for their respective vref voltage reference. the general topology of a chopped amplifier is shown in figure 6 . the cross signal is an internal on - chip signal and is not accessible on any pin or register. figure 6 : general topology of a chopped amplifie r g - + v inp v outp v outn v inn cross ab ab a b a b downloaded from: http:///
71m6545/71M6545H data sheet v2 21 it is assumed that an offset voltage voff appears at the positive a mplifier input. with all switches, as controlled by cross (an internal signal), in the a position, the output voltage is: voutp C voutn = g (vinp + voff C vinn) = g (vinp C vinn) + g voff with all switches set to the b position by applying the inverted cross signal, the output voltage is: voutn C voutp = g (vinn C vinp + voff) = g (vinn C vinp) + g voff, or voutp C voutn = g (vinp C vinn) - g voff thus, when cross is toggled, e.g., after each multiplexer cycle, the offset alt ernately appears on the output as positive and negative, which results in the offset effectively being eli minated, regardless of its polarity or magnitude. when cross is high, the connection of the amplifier input devices is revers ed. this preserves the overall polarity of that amplifier gain; it inverts its input offset. by alternately reversing the connection, the amplifiers offset is averaged to zero. this removes the most significant long - term drift mechanism in the voltage reference. the chop_e [1:0] ( i/o ram 0x2 106 [3:2] ) control field control s the behavior of cross. on the first ck32 rising edge after the last multiplexer state of its sequence, the multiplexer wait s one additional ck32 cycle before beginning a new frame. at the beginning of this cycle, the value of cross is updated according to the chop_e [1:0] field . the extra ck32 cycle allows time for the chopped vref to settle. during this cycle, muxsync is held h igh. the leading edge of muxsync initiates a pass through the ce program sequence . chop_e [1:0] has four states: positive, reverse, and two toggle states. in the positive state, chop_e [1:0] = 01, cross is held low. in the reverse state, chop_e [1:0] = 10, cr oss is held high. the two automatic toggling states are selected by setting chop_e=11 or chop_e=00. figure 7 : cross signal with chop_e = 00 figure 7 shows cross over two accumulation intervals when chop_e [1:0] = 00: at the end of the first in ter val, cross is high, at the end of the second interval, cross is low . operation with chop_e [1: 0] = 00 does not require control of the chopping mechanism by the mpu. in the second toggle state, chop_e [1:0] = 11, cross does not toggle at the end of the last multiplexer cycle in an accumulation interval . 2.2.8 71m6xx3 isolated sensor interface 2.2.8.1 general description non - isolating sensors, such as shunt resistors, can be connected to the inputs of the 71m6545/h via a combination of a pulse transformer and a 71m6xx3 ic (a top - level block diagram of this sensor interface is shown in figure 27 ). the 71m6xx3 receives power directly from the 71m6545/h via a pulse transformer and does not require a dedicated power supply circuit. the 71m6xx3 establishes 2 - way communication with the 71m6545/h , supplying current samples and auxiliary information such as sensor temperature via a serial data stream. up to three 71m6xx3 isolated sensor s can be supported by the 71m6545/h . when a remote sensor interface is enabled, the two analog current in puts become re - configured and a digital remote sensor interface. for example, when control bit rmt2 _e = 1, the i adc2 -i adc3 analog pins are re - configured as the digital interfac e pins to the remote sensor . each 71m6x x3 isolated sensor consists of the following building blocks: ? power supply that derives power from pulses received from the 71m6545/h ? bi - directional d igital communications interface downloaded from: http:///
71m6545/71M6545H data sheet 22 v2 ? shunt signal pre - amplifier ? 22 - bit 2nd order sigma - delta adc converter with p recision bandgap reference (chopping amplifier) ? temperature sensor (for digitally compensating vref) ? fuse system containing part - specific information during an ordinary mu ltiple x er cycle, the 71m6545/h internally determines which other channels are enabled with mux_div[3:0] (i/o ram 0x2100[7:4]) . at the same time, it decimate s the modulator output from the 71m6x x3 isolated sensors. each result is written to ce ram during one of its ce access time slots. 2.2.8.2 communication between 71m6545/h and 71m6x x3 isolate d sensor the adc of the 71m6x x3 derives its timing from the power pulses generated by the 71m6545/h and as a result, operates its adc slaved to the frequency of the power pulses . the generation of power pulses, as well as the communication protocol between the 71m6545/h and 71m6x x3 isolated sensor, is au tomatic and transparent to the user. details ar e not covered in this data sheet. 2.2.8.3 control of the 71m6x x3 isolated sensor the 71m6545/h can read or write certain types of information from each 71m6xx3 remote sensor. the data to be read is selected by a combination of th e rcmd[4:0] and tmuxrn[2:0] . to perform a read transaction from one of the 71m6xx3 devices, the mpu first writ es the tmuxrn[2:0 ] field (where n = 2, 4, 6, located at i/o ram 0x270a[2:0] , 0x270a[ 6:4] and 0x270 9 [2:0] , respectively ) . next, the mpu writes rcmd[4:0 ] ( sfr 0xfc[4:0] ) with the desired command and phase selection . when the rcmd[4:2] bits have cleared to zero, the transaction has been completed and the reques ted data is available in rmt _rd[15: 0] ( i/o ram 0x2602[7:0] is the msb and 0x2603[7:0] is the lsb) . the read pari ty error bit, perr _r d (sfr 0xfc[6]) is also updated during the transaction . if the mpu writes to rcmd[4:0] before a previously initiated read transaction is completed , the command is ig nored. therefore, the mpu must wait for rcmd[4:2] =0 before proceeding to issue the next remote sensor read command. the rcmd[4:0] field is divided into two sub - fields, command =rcmd[4:2] and phase =rcmd[1:0] , as shown in table 4 . table 4 . rcmd[4:0] bits command rcmd[4:2] phase selector rcmd[1:0] associated tmuxrn control field 000 invalid 00 invalid --- 001 command 1 01 iadc 2 -iadc3 tmuxr 2 [2:0] 010 command 2 10 iadc 4 -iadc5 tmuxr 4 [2:0] 011 reserved 11 iadc 6 -iadc7 tmuxr 6 [2:0] 100 reserved 101 invalid 110 reserved 111 reserved notes: 1. only two codes of rcmd[4:2 ] ( sfr 0x fc[4:2] ) are relevant for normal operation. these are rcmd[4:2 ] = 001 and 010. codes 000 and 101 are invalid and will be ignored if used. the remaining codes are re served and must not be used. 2. for the rcmd [1 :0 ] control field, codes 01, 10 and 11 are valid and 00 is invalid and must not be used. 3. the specific phase (a, b or c) associated with each tmuxrn[2:0] field, is de termined by how the iadcn input pins are connected in the meter design. table 5 shows the allowable combinations of values in rcmd[4:2 ] a nd tmuxrn[2:0 ] , and the corresponding data type and format s ent back by the 71m6xx3 remote s en sor and how the data is stored downloaded from: http:///
pds_6545_009 71m6545/71M6545H data sheet v2 23 in rmt_rd [15:8] and rmt_rd[7:0] . the mpu selects which of the three phases is read by asserting the proper code in the rcmd[1:0] field, as shown in table 4 . table 5: remote interface read commands rcmd[4:2] tmuxrn[2:0] read operation rmt_rd [15:8] rmt_rd [7:0] 001 00x trimt[7:0] ( trim fuse for all 71m6xx3) trimt[7]=rmt_rd[8] trimt[6:0]=rmt_rd[7:1] 001 11x trimbgb[7 :0] and trimbgd[7 :0] ( additional trim fuses for 71m6 11 3 and 71m6203 only ) trimbgb[7 :0] trimbgd[7 :0] 010 00x stemp[10:0] (sensed 71m6xx3 temperature) stemp[10:8]=rmt_rd[10:8] (rmt_rd[15: 11 ] are sign extended) stemp[7:0] 010 01x vsense[7 :0] (sensed 71m6xx3 supply voltage) all zeros vsense[7:0] 010 10x version[7:0] (chip version) version [7 :0] all zeros notes: 1. trimt[7:0] is the vref trim value for all 71m6xx3 devices . note that t he trimt[7:0] 8- bit value is formed by rmt_rd[8] and rmt_rd[7:1]. see the 71m6xxx data sheet for the equations related to trimt[7:0] and the corresponding temperature coefficient. 2. trimbgb[7:0] and trimbgd[7:0] are trim values used for characterizing the 71m6113 (0.5%) and 71m6203 (0.1%) over temperature. see the 71m6xxx data sheet for the equations r elated to trimbgb[7:0] and trimbgd[7:0] and the corresponding temperature coefficients. 3. see 2.5.6 71m6xx3 temperature sensor on page 54 . 4. see 2.5.8 71m6xx3 vcc monitor on page 55 . with hardware and trim - related information on each connected 71m6xx3 iso lated sensor available to the 71m6545/h , the mpu can implement temperature compensation of the energy measurement based on the individual temperature characteristics of the 71m6xx3 isolated sensors. see 4.5 metrology temperature compensation for details. table 6 shows all i/o ram registers used for control of the external 71m6x x3 isolated sensors. see the 71m6x x3 data sheet for additional details . downloaded from: http:///
71m6545/71M6545H data sheet 24 v2 table 6: i/o ram control bits for isolated sensor name addr ess rst default wake default r/w description rcmd[4:0] sfr fc[4:0] 0 0 r/w when the mpu writes a non - zero value to rcmd , the 71m6545/h issue s a command to the cor - responding isolated sensor selected with rcmd[1:0] . when the command is complete, the 71m6545/h clear s rcmd[4:2]. the command code itself is in rcmd[4:2 ]. perr_rd perr_wr sfr fc[6] sfr fc[5] 0 0 r/w the 71m6545/h set s these bits to indicate that a parity error on the isolated sensor has been de - tected. once set, the bits are re mem bered until they are cleared by the mpu. chopr[1:0] 2709[7:6] 00 00 r/w the chop settings for the is o la te d sensors. 00 C auto chop. change every multiplexer frame. 01 C positive 10 C negative 11 C same as 00 tmuxr2 [2:0] 270 a [2:0] 000 000 r/w the tmux bits for control of the isolated sen sor . tmuxr4 [2:0] 270 a[6:4] 000 000 r/w the tmux bits for control of the isolated sen sor . tmuxr6 [2:0] 270 9[2 :0] 000 000 r/w the tmux bits for control of the isolated sen sor . rmt _rd[15:8] rmt _rd[7:0] 2602[7:0] 2603[7:0] 0 0 r the read buffer for 71m6x x3 read operation s. rfly_dis 210c[3] 0 0 r/w controls how the 71m6545/h drives the 71m6x x3 power pulse. when set, the power pulse is driven high and low. when cleared, it is driven high followed by an open circuit flyback interval. rmt2 _e 2709[3] 0 0 r/w enables the isolated remote sensor interface and re - configures pins i adc2 - iadc3 as a balanced pair digital remote interface. rmt4 _e 2709[4 ] 0 0 r/w enables the isolated remote sensor interface and re - configures pins i adc4 - iadc5 as a balanced pair digital remote interface . rmt6 _e 2709[5 ] 0 0 r/w enables the isolated remote sensor interface and re - configures pins i adc6 - iadc7 as a balanced pair digital remote interface . refer to table 61 starting on page 88 for more complete details about these i/o ram locations. downloaded from: http:///
71m6545/71M6545H data sheet v2 25 2.3 digital computation engine (ce) the ce, a dedicated 32 - bit signal processor, performs the precision computations necessary to accurately measure energy. the ce calculations and processes include: ? multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied by the constant sample time). ? frequency - insensitive delay cancellation on all channels (to compensate for the delay bet ween samples caused by the multiplexing scheme). ? 90 phase shifter (for var calculations). ? pulse generation. ? monitoring of the input signal frequency (for frequency and phase information). ? monitoring of the input signal amplitude (for sag detecti on). ? scaling of the processed samples based on calibration coefficients. ? scaling of samples based on temperature compensation information. 2.3.1 ce program memory the ce program resides in flash memory. common access to flash mem ory by the ce and mpu is con tro lled by a memory share circuit. each ce instruction word is two bytes long. allocated flash space for the ce program cannot exceed 4096 16 - bit words (8 kb). the ce program counter begins a pass through the ce code each time multiplexer state 0 begins. the code pass ends whe n a halt instruction is executed. for proper operation, the code pass must be completed before the mul tiplexer cycle ends . the ce program must begin on a 1 kb boundary of the flash address. the i/o ram control field ce_lctn[ 5 :0] ( i/o ram 0x2109[5: 0] ) defines which 1 kb boundary contains the ce code. thus, the first ce instruction is located at 1024* ce_lctn[5 :0]. 2.3.2 ce data memory the ce and mpu share data memory (ram). common access to xram by the ce and mpu is controlled by a memory share circuit. the ce can access up to 3 kb of the 5 kb data ram (xram), i.e. from ram address 0x0000 to 0x0c00 . the xram can be accessed by the fir filter block , the rtm circuit, the ce, and the mpu. assigned time slots are re served for fir and mpu, respectively, to prevent bus contention for xram data access by the ce . the mpu read s and write s the xram shared between the ce and mpu as the primary means of data communication between the two processors. the ce is aided by support hardware to facilitate implementation of equations, pulse counters, and ac cumulators. this hardware is controlled through i/o ram field equ[2:0] (equation assist, i/o ram 0x2106[7:5] ), bit dio_pv (i/o ram 0x2457[6]), bit dio_pw (pulse count assist , i/o ram 0x2457[7] ), and sum_ samps [12:0] (accumulation assist , i/o ram 0x2107[4:0] and 0x2108[7:0] ). the integration time for each energy output, when using standard ce code, is sum_samps[12:0] /218 4 .53 (with mux_div[3:0] = 7 , i/o ram 0x2100[7:4] ). ce hardware issues the xfer_busy interrupt when the accumulation is complete. 2.3.3 ce communication with the mpu the ce outputs six signals to the mpu: ce_busy, xfer_busy, xpulse, ypulse, wpulse and vpulse . these are connected to the mpu interrupt service. ce_busy indicates t hat the ce is actively processing data. ce_busy occur s once every multiplexe r frame. xfer_busy indicates that the ce is updating to the o ut put region of the ce ram, which occur s whenever an accumulation cycle has been completed. both, ce_busy and xfer_busy are cleared when the ce executes a halt instruction. xpulse and ypulse can be configured to interrupt the mpu and indicate zero cr ossings of the mains voltage, sag failures , or other significant events. additionally, these signals can be connected directly to dio pins to provide di rect outputs f r om the ce. interrupts associated with these signals always occur on the leading edge. downloaded from: http:///
71m6545/71M6545H data sheet 26 v2 2.3.4 meter equations the 71m6545/h provide s hardware assistance to the ce in order to support various meter equat ions. this assistance is controlled through i/o ram field equ[2:0] (equation assist , i/o ram 0x2106[7:5] ) . the compute engine (ce) firmware for industrial configurations can implement the equations listed in table 7 . equ[2:0] specifies the equation to be used based on the meter configuration and on the number of phases used for metering. table 7 : inputs selected in multiplexer cycles equ[2:0] * description wh and varh formula recommended multiplexer sequence element 0 element 1 element 2 2 2- element, 3 - w, 3 delta va ia vb ib n/a ia va ib vb 3 2- element, 4 - w, 3 delta va(ia - ib)/2 vc ic n/a ia va ib vb ic vc 4 2- element, 4 - w, 3 wye va(ia - ib)/2 vb(ic - ib)/2 n/a ia va ib vb ic vc 5 3- element, 4 - w, 3 wye va ia vb ib vc ic ia va ib vb ic vc (id) note: * only equ[2:0] = 5 is supported by the currently available ce code versions for the 71m6545/h . contact your local maxim representative for ce codes that support equations 2, 3 and 4. 2.3.5 real - time monitor (rtm) the ce contains a real - time monitor (rtm), which can be programmed to monitor four selectable x ram locations at full sample rate. the data from the four monitored locations are serially output to the tmuxout pin via the digital output multiplexer at the beginning of each ce code pass. the rtm can be enabled and disabled with rtm_e (i/o ram 0x2106[1]) . the rtm output clock is avail able on the tmux2out pin . each rtm word is clocked out in 35 cycles and contains a leading flag bit. see figure 8 for the rtm output format. rtm is low when not in use. figure 8 : rtm timing 2.3.6 pulse generator s the 71m6545/h provide s fou r pulse generators, vpulse , wpulse, xpuls e and ypulse, as well as hardware support for the v pulse and wpulse pulse generators . the xpulse and ypulse genera tors are used by standard ce code to output ce status indicators, for example the status of the sag detection , to dio pins. all pulses can be configured to generate interrupts to the mpu. the polarity of the pulses may be inverted with pls_inv (i/o ram 0x210c[0]) . when this bit is set, the pulses are active high, rather than the more usual active low. pls_inv inverts all the pulse outputs. th e function of each pulse generator is determined by the ce code and the mpu code mu st configure the corresponding pulse outputs in agreement with the ce code. for example, standar d ce code produces a mains zero - crossing pulse on xpulse and a sag pulse on y pulse. cktest rtm flag rtm data0 (32 bits) lsb sign lsb sign rtm data1 (32 bits) lsb lsb sign sign rtm data2 (32 bits) rtm data3 (32 bits) 0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31 flag flag flag mux_state s mux_sync ck32 downloaded from: http:///
71m6545/71M6545H data sheet v2 27 a common use of the zero - crossing pulses is to generate interrupts in order to drive real - time clock software in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging. a common use for the sag pulse is to generate an interrupt that alerts the mpu when mains power is about to fail, so that the mpu code can store accumulated energy and other data t o eeprom before the v3p3sys supply voltage actually drops. 2.3.6.1 xpulse and ypulse pulses generated by the ce may be exported to the xpulse and ypulse pulse output pins . pins dio 6 and dio 7 are used for these pulses, respectively. generally, the xpulse and ypulse outputs can be updated once on each pass of the ce code . see 5.4 ce interface description on page 100 for details. 2.3.6.2 vpulse and wpulse referring to figure 9 , d uring each ce code pass the hardware stores exported wpulse and v pulse sign bits in an 8 - bit fifo and outputs them at a specified interval. this permits the ce code to calculate the vpulse and wpulse outputs at the beginning of its code pass and to rely on hardw are to spread them over the multiplexer frame. as seen in figure 9 , t h e fifo is reset at the beginning of each multiplexer frame. as also seen in figure 9 , t he i/o ram register pls_interval [7:0] (i/o ram 0x210b[7:0]) controls the delay to the first pulse up date and the interval between subsequent updates. the lsb of the pls_interval[7:0] register is equivalent to 4 ck_fir cycles (ck_fir is typically 4.9152mhz if pll_fast =1 and adc_div =0, but other ck_fir frequencies are possible; see the adc_div defi nition in table 61 . ) if pls_interval[7:0] =0 , the fifo is deactivated and the pulse output s are updated immediately. the mux frame duration in units of ck_fir clock cycles is given by : if pll_fast =1: mux frame duration in ck_fir cycles = [1 + ( fir_len +1) * ( adc_div +1) * ( mux_div )] * [150 / ( adc_div +1)] if pll_fast =0: mux frame duration in ck_fir cycles = [ 3 + 3*( fir_len +1) * ( adc_div +1) * ( mux_div )] * [48 / ( adc_div +1)] pls_interval[7:0] in units of ck_fir clock cycles is calculated by: pls_interval [7:0] = floor ( mux frame duration in ck_fir cycles / ce pulse updates per mux frame / 4 ) since the fifo resets at the beginning of each multiplexer frame, the user must specify pls_interva l[7:0] so that all of the possible pulse updates occurring in one ce execution are output before the multiplexer fram e completes. for instance, the 71m6545/h c e code outputs six updates per multiplexer interval, and if the multiplexer interval is 1950 ck_fir clock cycles long, the ideal value for the interval is 1950/6 /4 = 81.25 . however, i f pls_interval [7:0] = 82 , the six th output occur s too late and would be lost. in this case, the proper value for pls_interval [7:0] is 81 (i.e., round down the result) . since one lsb of pls_interval[7:0] is equal to 4 ck_fir clock cycles, the pulse time interval t i in units of ck_fir clock cycles is: t i = 4* pls_interval[7:0] if the fifo is enabled (i.e., pls_interval[7:0] 0), h ardware also provides a maximum pulse width feature in control register pls_max width[7:0] (i/o ram 0x210a) . by default, wpulse and vpulse are negative pulses (i.e., low level pulses, designed to sink current through an led). pls_maxwidth[7:0] determines the maximum negative pulse width t max in units of ck_fir clock cycles based on the pulse interval t i according to the formula: t max = (2 * pls_maxwidth [7:0] + 1) * t i if pls_maxwidth = 255 or pls_interval =0, no pulse width checking is performed, and the pulses default to 50% duty cycle. the polarity of the pulses may be inverted with the control bit pls_inv ( i/o ram 0x210c[0] ). when pls_inv i s set, the pulses are active high. the default value for pls_inv is zero, which selects active low pulses. downloaded from: http:///
71m6545/71M6545H data sheet 28 v2 the wpulse and v pulse pulse generator outputs are available on pins dio0/wpulse and dio1/vpulse , respectively (pins 45 and 44) . the pulses can also be output on opt_tx pin 53 (see opt_txe[1:0] , i/o ram 0x2456[3:2] for details). figure 9 . pulse generator fifo timing 2.3.7 ce functional overview the adc processes one sample per channel per multiplexer cycle. figure 10 shows the timing of the samples taken during one multiplexer cycle with mux_div[3:0] = 7 (i/o ram 0x2100[7:4]) . the number of samples processed during one accumulation cycle is controlled by the i/o ram register sum_samps[12:0] ( 0x2 1 07[4 :0] and 0x2108[7:0] ). the integration time for each energy output is : sum_samps[12:0] / 2184 .53 , w here 2184 .53 is the sample rate in hz for example, sum_samps[12:0] = 2184 establish es 2184 multiplexer cycl es per accumulation cycle or 2184/2184.53 = 0.9998 seconds . after an accumulation cycle is completed, the xfer_busy interrupt signals to the mpu that accumulated data are available. the slight difference between the nominal length of the accumulation interval (1000 ms) and the actual length of 999.8 ms ( 0.025%) is accounted for in the ce code and is of no practical consequence. ck32 mux_div conversions ( mux_div = 6 is shown) settle adc mux frame mux_sync 150 wpulse s 0 s 1 s 2 s 3 s 4 s 5 ce code rst w_fifo s 0 s 1 s 2 s 3 s 4 s 5 s 0 s 1 s 2 s 3 s 4 s 5 4* pls_interval 2. if wpulse is low longer than ( 2 *pls_maxwidth+1) updates , wpulse will be raised until the next low-going pulse begins. 3. only the wpulse circuit is shown. the varpulse circuit behaves identically. 4. all dimensions are in ck_fir cycles (4.92mhz). 5. if pls_interval =0, fifo does not perform delay. 4* pls_interval 4* pls_interval 4* pls_interval 4* pls_interval 4* pls_interval 1. this example shows how the fifo distributes 6 pulse generator updates over one mux frame. downloaded from: http:///
71m6545/71M6545H data sheet v2 29 figure 10 : samples from multiplexer cycle (frame) the end of each multiplexer cycle is signaled to the mpu by the ce_bu sy interrupt. at th e end of each multiplexer cycle , status information, such as sag data and the digitized input signal, is avai lable to the mpu. figure 11 : accumulation interval figure 11 shows the accumulation interval resulting from sum_samps[12:0] = 1 819 (i/o ram 0x2107[4:0] and 0x2108[7:0] ) , consisting of 1 819 sam ples of 45 7 .8 s each, followed by the xfer_busy interrupt. the sampling in this example is applied to a 50 hz signal. there is no correlation between the line signal frequency and the choice of sum _samps [12:0] . furthermore, sampling does not have to start when the line voltage crosses the zero line, and the le ngth of the accumulation interval need not be an integer mul tiple of the signal cycles. mux state ck32 (32768 hz) 0 3 1 2 mux_div = 7 conversions settle multiplexer frame (15 x 30.518 s = 457.8 s) s s ia va ib 30.5 s 61.04 s vb 61.04 s ic vc 4 5 6 61.04 s 61.04 s id xfer_busy interrupt to mpu 20ms 833ms downloaded from: http:///
71m6545/71M6545H data sheet 30 v2 2.4 80515 mpu core 2.4.1 mpu setup code for the proper operation of the 71m6545/h, it is necessary to have a small mp u program in flash memory. in a typical application, the external host processor performs all post - processing and monitors and controls the 71m6545/h over its spi slave interface. the following is a br ief description of the tasks performed by the required setup code . the setup code correctly configures the 71m6545/h to act as a n spi slave to a host processor, providing powerful afe and 32 - bit metrology processor functionality. ? the main objective of the setup code is to keep the mpu code execution confined to a s mall area of flash memory. ? m ost of the flash memory space is empty, except for the small setup program and the ce code. ? when ac power failure occurs, the mpu sets the sleep bit ( i/o ram 0x28b2[7] ) bit) to force the de vice to slp mode (see 3.2 slp mode (sleep mode) on page 66 ). ? sfr (special function registers) access is needed for configuring and contr olling the dio0 - dio14 pins. the sfr s of the mpu cannot be accessed directly over the spi slave interface . if the host requires control of dio0 - dio14, a small amount of code in the mpu provides the needed sfr access . ? triggering the wdt reset. ? controlling the 71m6xx3 remote sensor interfaces, if used (temperature data for ce). ? to speed up the start - up process and to offload the host processor, the small mpu program can implement the following optional steps at start - up: - copy ce data from flash to xram (default sett ings). - initialize the interrupt vector table. - initialize the pointer to the ce code location. - initialize the environmental settings for the ce code (multiplexer and filt er settings, etc.) - start the adc and ce. ? it is also recommended that the small mpu program maintains a counter t hat is incremented with each xfer_busy interrupt. by reading this counter, the external host processor can determine if any accumulated metrology data were missed and if the 71m6545/h code is executing as expected. sample mpu code that performs the se simple tasks is available from maxim . during normal operation, the host processor needs to trigger the watchdog reset periodically in order to avoid watchdog resets, if this is not done by the mpu program inside the 71m 6545/h. the remainder of this section provides detailed information concerning the mpu, and may be ignored if the application does not require the use of the mpu beyond t he simple setup code tasks described. 2.4.2 80515 mpu overview the 71m6545/h include s an 80515 mpu (8 - bit, 8051 - compatible) that processes most instructions in one clock cycle. using a 4.9 mhz clock results in a processing throughput of 4.9 mips. the 80515 arc hitecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. normally , a machine cycle is aligned with a memory fetch, therefore, most of the 1 - byte instructions are performed in a single machine cycle (mpu clock cycle) . this leads to an 8x average performance im prove ment (in terms of mips) over the intel ? 8051 device running at the same clock frequency . table 8 shows the ckmpu frequency as a function of the mck clock (19.6608 mhz) di vided by the mpu clock divider mpu_div[2:0] (i/o ram 0x2200[2:0]) . actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations, amr manageme nt, memory management and i/o management) using mpu_div[2:0] , as shown in table 8 . downloaded from: http:///
71m6545/71M6545H data sheet v2 31 table 8 : ckmpu clock frequencies mpu_div [2:0] ckmpu frequency 000 4.9152 mhz 001 2.4576 mhz 010 1.2288 mhz 011 614.4 k hz 100 307.2 khz 101 110 111 typical measurement and metering functions based on the results provided by the internal 32 - bit com pute engine (ce) are available for the mpu as part of the maxim demonstrati o n code, which is provided to help reduce the product design cycle . 2.4.3 memory organization and addressing the 80515 mpu core incorporates the harvard architecture with separate code and data spaces. mem ory organization in the 80515 is similar to that of the industry standard 8051. there are three memory areas: program memory (flash, shared by mpu and ce), external ram (data ram, shared by the ce and mpu, configuration or i/o ram ), and internal data memory (internal ram). table 9 shows the memory map. program memory the 80515 can address up to 64 kb of program memory space ( 0x 00 0 0 to 0xffff ) . program memory is read when the mpu fetches instructions or performs a movc operation. after reset, the mpu starts program execution from program memory loc ation 0x0000. the lower part of the program memory includes reset and interrupt vectors. the interrupt vectors are spaced at 8 - byte in tervals, starting from 0x0003. mpu external data memory (xram) both internal and external memory is physically located on the 71m6545/h device . the e x ternal mem ory referred to in this documentation is only external to the 80515 mpu core. 5 kb of ram starting at address 0x0000 is shared by the ce and mpu. the ce normally uses the first 1 kb, leaving 4 kb for the mpu. different versions of the ce code use varying amounts. consult the documentation for the specific code version being used for the exact limit. if the mpu overwrites t he ces working ram, the ces output may be corrupted. if th e ce is dis abled, the first 0x40 bytes of ram are still unusable while mux_ div[3:0] 0 (i/o ram 0x2100[7: 3] ), because the 71m6545/h adc writes to these locations. writing mux_ div[3:0] = 0 disables the adc output, preventing the ce from writing the first 0x40 by tes of ram. to change the slot assignments established by muxn_sel[3:0] , first set mux_div[3:0] to zero, then change the muxn_sel[3:0] slot assignments, and finally set mux_di v[3:0] to the number of active mux frame slots . the 80515 writes into external data memory when the mpu executes a movx @ri,a or movx @ dptr ,a instruction. the mpu reads external data memory by executing a movx a, @ri or movx a,@ dptr instruction ( pdata, sfr 0xb f , provides the upper 8 bytes for the movx a,@ri instruction) . downloaded from: http:///
71m6545/71M6545H data sheet 32 v2 internal and external memory map table 9 shows the address, type, use and size of the various memory components. table 9 : memory map address (hex) memory technology memory type name typical usage memory size (bytes) 0000 -ffff flash memory non - volatile program memory mpu program and non - volatile data 64 kb ce program (on 1 kb boundary) 3 kb max. 0000 - 13 ff static ram volatile external ram (xram) shared by ce and mpu 5 kb 2000 - 27 ff static ram volatile configuration ram (i/o ram ) hardware control 2 kb 2800 - 28 7f static ram non - volatile (battery) configuration ram ( i/o ram ) battery - buffered memory 12 8 0000 - 00ff static ram volatile internal ram part of 80515 core 256 movx addressing there are two types of instructions differing in whether they provide an 8 - bit or 16 - bit indirect address to the external data ram. in the first type, movx a,@ri, the contents of r0 or r1 in the current register bank provide the eight lower - ordered bits of address. the eight high - ordered bits of the address are specified with the pdata sfr. this method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external data ram. in the second type of movx instruction, movx a,@dptr, the data pointer g enerates a 16 - bit address. this form is faster and more efficient when accessing very large data arr ays (up to 64 kb ), since no additional instructions are needed to set up the eight high ordered bits of the address . it is possible to mix the two movx types. this provides the user wi th four separate data pointers, two with direct access and two with paged access, to the entire 64 kb of exter nal memory range. dual data pointer the dual data pointer accelerates the block moves of data. the standard dptr is a 16 - bit register that is used to address external memory or peripherals. in the 80515 core, the st andard data pointer is called dptr , the second data pointer is called dptr1 . the data pointer select bit, located in the lsb of the dps register ( dps [0] , s fr 0x92 ) , chooses the active pointer. dptr is selected when dps [0] = 0 and dptr1 is selected when dps [0] = 1. the user switches between pointers by toggling the lsb of the dps register. the values in the data pointers are not affected by the lsb of the dps register. all dptr related instructions use the currently selected dptr for any activity. the second data pointer may not be supported by certain compilers. dptr1 is useful for copy routines, where it can make the inner loop of the routine two inst ructions faster compared to the reloading of dptr from registers . any interrupt routine using dptr1 must save and restore dps , dptr and dptr1 , which increases stack usage and slows down interrupt latency. by selecting the evatronics r80515 core in the ke il compiler project settings and by using the compiler directive modc2, dual data pointers are enabled in certain library routines. an alternative data pointer is available in the form of the pdata register ( sfr 0xbf ) , sometimes referred to as usr2 ) . it defines the high byte of a 16 - bit address when reading or writing xdata with the instruction movx a,@ri or movx @ri,a. downloaded from: http:///
71m6545/71M6545H data sheet v2 33 internal data memory map and access the internal data memory provides 256 bytes (0x00 to 0xff) of data memory . the internal data memo ry address is always 1 byte wide . table 10 shows the internal data memory map. the special function registers (sfr) occupy the upper 128 bytes. the sfr are a of internal data memory is available only by direct addressing . indirect addressing of this area accesses the upper 128 bytes of internal ram . the lower 128 bytes contain working registers and bit addressable memory . the lower 32 bytes form four banks of eight registers (r0 - r7) . two bits on the program memory status word ( p sw , sfr 0xd0 ) select which bank is in use . the next 16 bytes form a block of bit addressable memory space at ad dresse s 0x00 - 0x7f . all of the bytes in the lower 128 bytes are accessible through direct or indir ect addressing . table 10 : internal data memory map address range direct addressing indirect addressing 0x80 0xff special function registers (sfrs) ram 0x30 0x7f byte addressable area 0x20 0x2f bit addressable area 0x00 0x1f register banks r0r7 2.4.4 special function registers (sfrs) a map of the special function registers is shown in table 11 . only a few addresses in the sfr memory space are occupied, the others are not implemented. a read access to unimplemented addresses return s undefined data, while a write access ha s no eff ect. sfrs specific to the 71m6545/h are shown in bold print on a gray field . the registers at 0x80, 0x88, 0x90, etc., are bit a ddressable, all others are byte addressable. table 11 : special function register map hex/ bin bit addressable byte addressable bin/ hex x000 x001 x010 x011 x100 x101 x110 x111 f8 flag1 stat remote0 spi1 ff f0 b f7 e8 iflags ef e0 a e7 d8 wdcon df d0 psw d7 c8 t2con cf c0 ircon c7 b8 ien1 ip1 s0relh s1relh pdata bf b0 p3 flshctl pgadr b7 a8 ien0 ip0 s0rell af a0 p2 dir2 dir0 a7 98 s0con s0buf ien2 s1con s1buf s1rell eedata eectrl 9f 90 p1 dir1 dps erase 97 88 tcon tmod tl0 tl1 th0 th1 ckcon 8f 80 p0 sp dpl dph dpl1 dph1 pcon 87 downloaded from: http:///
71m6545/71M6545H data sheet 34 v2 2.4.5 generic 80515 special function registers table 12 shows the location, description and reset or power - up value of the generic 80515 sfrs . additional descriptions of the registers can be found at the page numbers listed in the table. table 12 : generic 80515 sfrs - location and reset values name address (hex) reset value (hex) description page (s) p0 0x80 0xff port 0 36 sp 0x81 0x07 stack pointer 35 dpl 0x82 0x00 data pointer low 0 35 dph 0x83 0x00 data pointer high 0 35 dpl1 0x84 0x00 data pointer low 1 35 dph1 0x85 0x00 data pointer high 1 35 pcon 0x87 0x00 uart speed control 38 tcon 0x88 0x00 timer/counter control 41 tmod 0x89 0x00 timer mode control 39 tl0 0x8a 0x00 timer 0, low byte 39 tl1 0x8b 0x00 timer 1, high byte 39 th0 0x8c 0x00 timer 0, low byte 39 th1 0x8d 0x00 timer 1, high byte 39 ckcon 0x8e 0x01 clock control (stretch=1) 36 p1 0x90 0xff port 1 36 dps 0x92 0x00 data pointer select register 32 s0con 0x98 0x00 serial port 0, control register 38 s0buf 0x99 0x00 serial port 0, data buffer 36 ien2 0x9a 0x00 interrupt enable register 2 41 s1con 0x9b 0x00 serial port 1, control register 38 s1buf 0x9c 0x00 serial port 1, data buffer 36 s1rell 0x9d 0x00 serial port 1, reload register, low byte 36 p2 0xa0 0xff port 2 36 ien0 0xa8 0x00 interrupt enable register 0 41 ip0 0xa9 0x00 interrupt priority register 0 43 s0rell 0xaa 0xd9 serial port 0, reload register, low byte 36 p3 0xb0 0xff port 3 36 ien1 0xb8 0x00 interrupt enable register 1 41 ip1 0xb9 0x00 interrupt priority register 1 43 s0relh 0xba 0x03 serial port 0, reload register, high byte 36 s1relh 0xbb 0x03 serial port 1, reload register, high byte 36 pdata 0xbf 0x00 high address byte for movx@ri - also called usr2 32 ircon 0xc0 0x00 interrupt request control register 42 t2con 0xc8 0x00 polarity for int2 and int3 42 psw 0xd0 0x00 program status word 35 wdcon 0xd8 0x00 baud rate control register (only wdcon[ 7] bit used) 36 a 0xe0 0x00 accumulator 35 b 0xf0 0x00 b register 35 downloaded from: http:///
71m6545/71M6545H data sheet v2 35 accumulator ( acc , a , sfr 0x e0 ): acc is the accumulator register . most instructions use the accumulator to hold the operand . the mnemonics for accumulator - specific instructions refer to accumulator as a , not acc . b register ( sfr 0xf0 ) : the b register is used during multiply and divide instructions . it can also be used as a scratch - pad register to hold temporary data. program status word ( p sw , sfr 0xd0 ): this register contains various flags and control bits for the selection of t he register banks (see table 13 ). table 13 : psw bit functions ( sfr 0xd0 ) psw bit symbol function 7 cv carry flag . 6 ac auxiliary carry flag for bcd operations . 5 f0 general purpose flag 0 available for user. f0 is not to be confused with the f0 flag in the cestatus register. 4 rs1 register bank select control bits . the contents of rs1 and rs0 select the working register bank: rs1/rs0 bank selected location 00 bank 0 0x00 C 0x07 01 bank 1 0x08 C 0x0f 10 bank 2 0x10 C 0x17 11 bank 3 0x18 C 0x1f 3 rs0 2 ov overflow flag . 1 C user defined flag . 0 p parity flag, affecte d by hardware to indicate odd or even number of one bits in the accumulator, i.e. even parity. s tack pointer ( sp , sfr 0x8 1 ) : the stack pointer is a 1 - byte register initialized to 0x07 after reset . this register is incremented before push and call instructions, causing the stack to begin at location 0x08. data pointer: the data pointer s ( dptr and dprt1 ) are 2 bytes wide. the lower part is dpl (sfr 0x82) and dpl1 (sfr 0x84), respectively . t he highest is dph (sfr 0x83) and dph1 (sfr 0x85), respectively . the data pointers can be loaded as two registers (e.g. mov dpl,#data8). they are generally used to access external code or data space (e.g. movc a,@a+dptr or movx a,@dptr respecti vely). program counter: the program counter ( pc ) is 2 bytes wide and initialized to 0x0000 after reset . this register is incremented when fetching operation code or when operating on data from program memory . port registers: dio 0 through dio1 4 are controlled by special function registers p0 , p1, p2 , and p3 as shown in table 14 . a bove dio1 4 , the dio n [ ] registers in i/o ram are used. since the direction bits are contained in the upper nibble of each sfr pn register and the dio bits are contained in the lower nibble, it is possible to configure the direction of a given dio pin and set its ou t put value with a single write operation, thus facilitating the implementation of bit - banged interfaces. writing a 1 t o a dio_dir bit configures the corresponding dio as an output, while writing a 0 configures it as an input. writing a 1 to a dio bit causes the corresponding pin to be at hi gh level (v3p3) , while w riting a 0 causes the corresponding pin to be held at a l ow level (gnd) . downloaded from: http:///
71m6545/71M6545H data sheet 36 v2 table 14 : port registers (dio0 -14) sfr name sfr address d7 d6 d5 d4 d3 d2 d1 d0 p0 80 dio_dir[3:0] dio[3:0] p1 90 dio_dir[ 7:4] dio[7:4] p2 a0 dio_dir[ 11 :8] dio[11:8] p3 b0 dio_dir[ 14: 12 ] dio[1 4 :11] all dio ports on the chip are bi - directional . each of them consists of a l atch (sfr p0 to p3 ) , an output driver and an input buffer, therefore the mpu can output or read data through any of these por ts . even if a dio pin is configured as an output, the state of the pin can still be read by the mpu, for example when counting pulses issued via dio pins that are under ce control. at power - up dio0 - 14 are configured as outputs, but the pins are in a high - impedance state because port_e=0 (i/o ram 0x270c[5]) . host firmware should first configure dio0 - 14 to the desired state, then set port_e=1 to enable the function. clock stretching ( ckcon[2:0], sfr 0x8e ) the ckcon[2:0] field define s the stretch memor y cycles that are used for movx instructions when access ing external peripherals. the practical value of this register for the 71m6545/h is to guarantee access to xram between ce, mpu, and spi . table 15 shows how the signals of the external memory interface change when stretch val ues are set from 0 to 7. the widths of the signals are counted in mpu clock cycle s. the post - reset state of t he ckcon[2:0] field (001) , which is shown in bold in the table, performs the movx instructions with a stretch value equal to 1. table 15 : stretch memory cycle width ckcon[2:0] stretch value read signal w idth write s ignal w idth memaddr memrd memaddr memwr 000 0 1 1 2 1 001 1 2 2 3 1 010 2 3 3 4 2 011 3 4 4 5 3 100 4 5 5 6 4 101 5 6 6 7 5 110 6 7 7 8 6 111 7 8 8 9 7 2.4.6 instruction set all instructions of the generic 8051 microcontroller are supported . a complete list of the instruction set and of the associated op - codes is contained in the 71m65 4x software users guide (sug) . 2.4.7 uarts the 71m6545/h include s a uart (uart0) that can be programmed to communicate with a variety of amr modules and other external devices . the uart is a dedicated 2 - wire serial interface, which can communicate with an external host processor at up to 38,400 bits/s (with mpu clock = 1.2288 mhz) . the operation of the rx and tx uart0 pins is as follows: downloaded from: http:///
71m6545/71M6545H data sheet v2 37 ? uart0 rx: s erial input data are applied at this pin . conforming to rs - 232 standard, the bytes are input lsb first. ? uart0 tx : this pin is used to output the serial data . the bytes are output lsb first. the 71m6545/h has several uart - related registers for the control and buffering of serial data . a single sfr register serves as both the transmit buffer and receive buffer ( s0buf , sfr 0x99 for uart0). when written by the mpu, sxbuf acts as the transmit buffer, and when read by the mpu, it acts as the receive buffer. writing data to the transmit buffer starts the transmission by the uart. received data are available by reading from the receive buffer. the uart can simultaneously transmit and receive data. wdcon [7] (sfr 0xd8) selects whether timer 1 or the internal baud rate generator is used . all uart transfers are pro grammable for parity enable, parity, 2 stop bits/1 stop bit and xon/x off options for variable commu nication baud rates from 300 to 38400 bps . table 16 shows how the baud rates are calculated . table 17 shows the selectable uart operation modes. table 16 : baud rate generation using timer 1 ( wdcon [7] = 0) using internal baud rate generator ( wdcon [7] = 1) uart0 2 smod * f ckmpu / (384 * (256 - th1 )) 2 smod * f ckmpu /(64 * (2 10 - s0rel )) uart1 n/a f ckmpu /(32 * (2 10 - s1rel )) s0rel and s1rel are 10 - bit values derived by combining bits from the respective timer reload regis ters . ( s0rell, s0relh, s1rell, s1relh are sfr 0xaa, sfr 0xba, sfr 0x9d and sfr 0xbb , respectively) smod is the smod bit in the sfr pcon register ( sfr 0x87 ) . th1 (sfr 0x8d) is the high byte of timer 1. table 17 : uart modes uart 0 uart 1 mode 0 n/a start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) mode 1 start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1) start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator) mode 2 start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of f ckmpu n/a mode 3 start bit, 8 data bits, parity, stop bit, va riable baud rate (internal baud rate generator or timer 1) n/a parity of serial data is available through the p flag of the accumulator . 7- bit serial modes with parity, such as those used by the flag protocol, can be simulated by setting an d reading bit 7 of 8- bit output data . 7- bit serial modes without parity can be simulated by setting bit 7 to a constant 1 . 8- bit serial modes with parity can be simulated by setting and reading the 9 th bit, using the control bits tb80 ( s0con [ 3 ] ) and tb81 ( s1con [3] ) in the s0co n ( sfr 0x98 ) and s1con ( sfr 0x9b ) registers for transmit and rb81 ( s1con [2] ) for receive operations . all supported operation modes use oversampling for the incoming bit stream when re ceiving data. each bit is sampled three times at the projected middle of the bit duration. this technique allows for deviations of the received baud rate from nominal of up to 3.5%. the feature of receiving 9 bits (mode 3 for uart0) can be used as h andshake signals for inter - processor communication in multi - processor systems. in this case, the slave processors have bit sm20 ( s0con[5] ) for uart0, set to 1. when the master processor outputs the slaves address, it sets the 9 th bit to 1, causing a serial port receive interrupt in all the slaves. the slave proces sors compare the received byte with their address. if there is a match, the addressed slave clear s sm20 or sm21 an d receive the rest of the message. downloaded from: http:///
71m6545/71M6545H data sheet 38 v2 the rest of the slave s ignore the message. after addressing the slave, the host outputs the rest of the message with the 9 th bit set to 0, so no additional serial port receive interrupts is generated. uart control regis ters: the function s of uart0 depend on the setting of the serial port control register s0con shown in table 18 , and the pcon register shown in table 19 . since the ti0 and ri0 bits are in an sfr bit addressable byte, common practice would be to clear them with a bit operation, but this must be avoided . the hardware implements bit operations as a byte wide read - modify - write hardware macro. if an interrupt occurs after the read , but before the write, its flag is cleared unintentionally. the proper way to clear these flag bits is to write a byte mask consist ing of all ones except for a zero in the location of the bit to be cleared. the flag bits are configured i n hardware to ignore ones written to them. table 18 : the s0con (uart0) register ( sfr 0x98 ) bit symbol function s0con [7] sm0 the sm0 and sm1 bits set the uart0 mode: mode description sm0 sm1 0 n/a 0 0 1 8- bit uart 0 1 2 9- bit uart 1 0 3 9- bit uart 1 1 s0con [6] sm1 s0con [5] sm20 enables the inter - processor communication feature. s0con[4] ren0 if set, enables serial reception. cleared by software to disable reception. s0con[3] tb80 the 9th transmitted data bit in modes 2 and 3. set or cleared by the mpu, depending on the function it performs (parity check, multiprocessor communication etc.) s0con[2] rb80 in modes 2 and 3 it is the 9 th data bit received. in mode 1, sm20 is 0, rb80 is the stop bit. in mode 0, this bit is not used. must be cleared by software. s0con[1] ti0 transmit interrupt flag; set by hardware after completion of a serial t ransfer. must be cleared by software (see caution above) . s0con[0] ri0 receive interrupt flag; set by hardware after completion of a serial reception. must be cleared by software (see caution above) . table 19 : pcon register bit description ( sfr 0x87 ) bit symbol function pcon[7] smod the smod bit doubles the baud rate when set 2.4.8 timers and counters the 80515 has two 16 - bit timer/counter registers: timer 0 and timer 1 . these registers can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle, i.e. , it counts up once for every 12 periods of the mpu clock. in counter mode, the register is incremented when the falling edge is observed at the corres ponding input signal t0 or t1 (t0 and t1 are the timer gating inputs derived from certain dio pins . since it takes 2 machine cycles to recognize a 1- to - 0 event, the maximum input count rate is 1/2 of the cl o ck frequency (ckmpu) . there are no restrictions on the duty cycle, however to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycl e. four operating modes can be selected for timer 0 and timer 1, as shown in table 20 and table 21 . the tmod ( sfr 0x89 ) r egister, shown in table 22 , is used to select the appropriate mode. the timer/counter operation is controlled by the tcon ( sfr 0x88 ) r egister, which is shown in table 23 . bits tr1 ( tcon [6] ) and tr0 ( tcon [4] ) in the tcon register start their associated timers when set. downloaded from: http:///
71m6545/71M6545H data sheet v2 39 table 20 : timers/counters mode description m1 m0 mode function 0 0 mode 0 13 - bit counter/timer mode with 5 lower bits in the tl0 or tl1 ( sfr 0x8a or sfr 0x8b ) register and the remaining 8 bits in the th0 or th1 ( sfr 0x8c or sfr 0x8d ) register (for timer 0 and timer 1, respectively) . the 3 high order bits of tl0 and tl1 are held at zero. 0 1 mode 1 16 - bit counter/timer mode . 1 0 mode 2 8- bit auto - reload counter/timer . the reload value is kept in th0 or th1 , while tl0 or tl1 is incremented every machine cycle . when tl( x) overflows, a value from th( x) is copied to tl (x) (where x is 0 for counter/timer 0 or 1 for counter/timer 1 . 1 1 mode 3 if tim er 1 m1 and m0 bits are set to 1, timer 1 stops . if t im er 0 m1 and m0 bits are set to 1, timer 0 acts as two in dependent 8- bit timer/counters. in mode 3, tl0 is affected by tr0 and gate control bits, and sets the tf0 flag on overflow, while th0 is affected by the tr1 bit, and the tf1 flag is set on overflow. table 21 specifies the combinations of operation modes allowed for timer 0 and timer 1. table 21 : allowed timer /counter mode combinations timer 1 mode 0 mode 1 mode 2 timer 0 - mode 0 y es y es y es timer 0 - mode 1 y es y es y es timer 0 - mode 2 not allowed not allowed y es table 22 : tmod register bit description (sfr 0x89) bit symbol function timer/counter 0: tmod[7] gate if tmod[7] is set, external input signal control is enabled for counter 0. the tr0 bit in the tcon register ( sfr 0x88 ) must also be set in order for counter 0 to increment. with these settings, counter 0 increment s on every falling edge of the logic signal applied to one or more of the dio 2- 11 pins, as specified by the contents of the dio_r2 through dio_r11 registers. see table 47 . tmod[6] c/t selects timer or counter operation. when set to 1, a counter operation is performed. when cleared to 0, the corresponding register function s as a timer. tmod[5:4] m1:m0 selects the mode for timer/counter 0 as shown in table 20 . timer/counter 1 tmod[3] gate if tmod[ 3] is set, external input signal control is enabled for counter 1. the tr1 bit in the tcon register ( sfr 0x88 ) must also be set in order for counter 1 to increment. with these settings, counter 1 increment s on every falling edge of the logic signal applied to one or more of the dio 2- 11 pins, as specified by the contents of the dio_r2 through dio_r11 registers. see table 47 . tmod[2] c/t selects timer or c ounter operation. when set to 1, a counter operation is performed. when cleared to 0, the correspondi ng register function s as a t imer. tmod[1:0] m1:m0 selects the mode for timer/counter 1, as shown in table 20 . downloaded from: http:///
71m6545/71M6545H data sheet 40 v2 table 23 : the tcon register bit functions (sfr 0x88) bit symbol function tcon[7] tf1 the timer 1 overflow flag is set by hardware when timer 1 overflows. this flag can be cleared by software and is automatically cleared when an interrupt is processed. tcon[6] tr1 timer 1 run control bit. if cleared, timer 1 stops. tcon[5] tf0 timer 0 overflow flag set by hardware when timer 0 overflows. this fl ag can be cleared by software and is automatically cleared when an interrupt is processed. tcon[4] tr0 timer 0 run control bit. if cleared, timer 0 stops. tcon[3] ie1 interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. cleared when an interrupt is processed. tcon[2] it1 interrupt 1 type control bit. selects either the falling edge or low level on input pin to cause an interrupt. tcon[1] ie0 interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. cleared when an interrupt is processed. tcon[0] it0 interrupt 0 type control bit. selects either the falling edge or low level on input pin to cause interrupt. 2.4.9 wd timer (software watchdog timer) there is no internal software watchdog timer . use the standard hardware watchdog timer instead (see 2.5.13 hardware watchdog timer ). 2.4.10 interrupts the 80515 provides 11 interrupt sources with four priority levels . each source has its own interrupt r equest flag(s) located in a special function register ( tcon , ircon , and scon ) . each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in ien0 (sfr 0xa8) , i en1 (sfr 0xb8) , and ien2 (sfr 0x9a) . figure 12 shows the device interrupt structure. referring to figure 12 , interrupt sources can originate from within the 80515 mpu core (referred to a s in ternal sources) or can originate from other parts of the 71m6545/h metrology processor (referred to as external sources). there are seven external interrupt sources, as seen in the le ftmost part of figure 12 , and in table 24 and table 25 (i.e., ex0-ex6 ). i nterrupt overview when an interrupt occurs, the mpu vector s to the predetermined address as shown in table 36 . once the interrupt service has begun, it can be interrupted only by a higher pri ority interrupt . the interrupt service is terminated by a return from instruction, reti . when an reti is performed, the processor return s to the instruction that would have been next when the interrupt occurred. when the interrupt condition occurs, the processor also indicate s this by setting a flag bit . this bit is set regardless of whether the interrupt is enabled or disabled . each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware . if the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set . on the next instruction cycle, the interrupt is acknowledged by hardware forcing an lcall to the appropriate vector address, if the following conditions are met: ? no interrupt of equal or higher priority is already in progress. ? an instruction is currently being executed and is not completed. ? the instruction in progress is not reti or any write access to the regi sters ien0 , ien1 , ien2 , ip0 or ip1 . special function registers for interrupts the following sfr registers control the interrupt functions: ? the interrupt enable registers: ien0, ien1 and ien2 (see table 24 , table 25 an d table 26 ). ? the timer/counter control registers, tcon and t2con (see table 27 and table 28 ). downloaded from: http:///
71m6545/71M6545H data sheet v2 41 ? the interrupt request r egister , ircon (see table 29 ). ? the interrupt priority registers: ip0 and ip1 (see table 34 ). table 24 : the ien0 bit functions (sfr 0xa8) bit symbol function ien0 [7] eal eal = 0 disable s all interrupts . ien0 [6] C not used . ien0 [5] C not used . ien0 [4] es0 es0 = 0 disable s serial channel 0 interrupt . ien0 [3] et1 et1 = 0 disable s timer 1 overflow interrupt . ien0 [2] ex1 ex1 = 0 disable s external interrupt 1 . ien0 [1] et0 et0 = 0 disable s timer 0 overflow interrupt . ien0 [0] ex0 ex0 = 0 disable s external interrupt 0 . table 25 : the ien1 bit functions (sfr 0xb8) bit symbol function ien1 [7] C not used. ien1 [6] C not used. ien1 [5] ex6 ex6 = 0 disable s external interrupt 6 . ien1 [4] ex5 ex5 = 0 disable s external interrupt 5 . ien1 [3] ex4 ex4 = 0 disable s external interrupt 4 . ien1 [2] ex3 ex3 = 0 disable s external interrupt 3 . ien1 [1] ex2 ex2 = 0 disable s external interrupt 2 . ien1 [0] C not used . table 26 : the ien2 bit functions (sfr 0x9a) bit symbol function ien2[0] es1 es1 = 0 disable s the serial channel 1 interrupt . table 27 : tcon bit functions (sfr 0x88) bit symbol function tcon[7] tf1 timer 1 overflow flag . tcon[6] tr1 not used for interrupt control . tcon[5] tf0 timer 0 overflow flag . tcon[4] tr0 not used for interrupt control . tcon[3] ie1 external interrupt 1 flag . tcon[2] it1 external interrupt 1 type control bit : 0 = interrupt on low level. 1 = interrupt on falling edge. tcon[1] ie0 external interrupt 0 flag tcon[0] it0 external interrupt 0 type control bit : 0 = interrupt on low level. 1 = interrupt on falling edge. downloaded from: http:///
71m6545/71M6545H data sheet 42 v2 table 28 : the t2con b it functions (sfr 0xc8) bit symbol function t2con[7] C not used. t2con[6] i3fr polarity control for int3: 0 = falling edge. 1 = rising edge. t2con[5] i2fr polarity control for int2: 0 = falling edge. 1 = rising edge. t2con[4:0] C not used. table 29 : the ircon bit functions (sfr 0xc0) bit symbol function ircon[7] C not used ircon[6] C not used ircon[5] iex6 1 = external interrupt 6 flag . irco n[4] iex5 1 = external interrupt 5 flag . ircon[3] iex4 1 = external interrupt 4 flag . ircon[2] iex3 1 = external interrupt 3 flag . ircon[1] iex2 1 = external interrupt 2 flag . ircon[0] C not used. tf0 and tf1 (timer 0 and timer 1 overflow flag s ) is automatically cleared by hardware when the service routine is called (signals t0ack and t1ack C port isr C active high when the service routine is called). ie0, ie1 and iex2 - iex6 are cleared automatically when hardware causes execution to vector to the interrupt service routine. external mpu interrupts the seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71m6545/h , for example the ce, dio, rtc, or eeprom interface. the external interrupts are connected as shown in table 30 . the po larity of interrupts 2 and 3 is programmable in the mpu via the i3fr and i2fr bits in t2con (sfr 0xc8) . interrupts 2 and 3 should be programmed for falling sensitivity ( i3fr = i2fr = 0). the generic 8051 mpu literature states that interrupts 4 through 6 are defined as rising - edge sensi tive. thus, the hardware signals attached to interrupts 5 and 6 are in verted to achieve the edge polarity shown in table 30 . table 30 : external mpu interrupts external interrupt connection polarity flag reset 0 digital i/o (ie0) automatic 1 digital i/o (ie1) automatic 2 ce_pulse (ie_xpulse, ie_ypulse, ie_wpulse, ie_vpulse) rising manual 3 ce_busy (ie3) falling automatic 4 vstat ( vstat[2:0] changed ) (ie4) rising automatic 5 eeprom busy (falling), spi (rising) (ie_eex, ie_spi) C manual 6 xfer_busy (falling), rtc_1sec, rtc_1min, rtc_t (ie_xfer, ie_rtc1s, ie_rtc1m, ie_rtct) falling manual external interrupt 0 and 1 can be mapped to pins on the device using dio resource maps. downloaded from: http:///
71m6545/71M6545H data sheet v2 43 sfr enable bits must be set to permit any of these interrupts to occur . likewise, each interrupt has its own flag bit, which is set by the interrupt hardware, and reset by the m pu interrupt handler . xfer_busy, rtc_1sec, rtc_1min , rtc_ t , spi, pllrise and pllfall have their own enable and flag bits in addition to the interrupt 6, 4 and enable and flag bits (see table 31 : interrupt enable and flag bits ). ie0 through iex6 are cleared automatically when the hardware vectors to the interrupt handler . the other flags, ie_xfer through ie_pb , are cleared by writing a zero to them . since these bits are in an sfr bit addressable byte, common practice would be to clear them with a bit operation, but this must be avoided . the hardware implements bit operations as a byte wide read - modify - write hardware macro . if an interrupt occurs after the read, but before the write, its flag is cleared un intentionally . the proper way to clear the flag bits is to write a byte mask consisti ng of all ones except for a zero in the location of the bit to be cleared . the flag bits are configured in hardware to ignore ones written to them. table 31 : interrupt enable and flag bits interrupt enable interrupt flag interrupt description n ame location name location ex0 sfr a8[[0] ie0 sfr 88[1] external interrupt 0 ex1 sfr a8[2] ie1 sfr 88[3] external interrupt 1 ex2 sfr b8[1] iex2 sfr c0[1] external interrupt 2 ex3 sfr b8[2] iex3 sfr c0[2] external interrupt 3 ex4 sfr b8[3] iex4 sfr c0[3] external interrupt 4 ex5 sfr b8[4] iex5 sfr c0[4] external interrupt 5 ex6 sfr b8[5] iex6 sfr c0[5] external interrupt 6 ex_xfer ex_rtc1s ex_rtc1m ex_rtct ex_spi ex_eex ex_xpulse ex_ypulse ex_wpulse ex_vpulse 2700[0] 2700[1] 2700[2] 2700[4] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] ie_xfer ie_rtc1s ie_rtc1m ie_rtc t ie_spi ie_eex ie_xpulse ie_ypulse ie_wpulse ie_vpulse sfr e8[0] sfr e8[1] sfr e8[2] sfr e8[4] sfr f8[7] sfr e8[7] sfr e8[6] sfr e8[5] sfr f8[ 6] sfr f8[ 5] xfer_busy interrupt (int 6) rtc_1sec interrupt (int 6) rtc_1min interrupt (int 6) rtc_ t interrupt (int 6) spi interrupt eeprom interrupt ce_xpulse interrupt (int 2) ce_ypulse interrupt (int 2) ce_wpulse interrupt (int 2) ce_vpulse interrupt (int 2) interrupt priority level structure all interrupt sources are combined in groups, as shown in table 32 . table 32 : interrupt priority level groups group group members 0 external interrupt 0 serial channel 1 interrupt 1 timer 0 interrupt external interrupt 2 2 external interrupt 1 external interrupt 3 3 timer 1 interrupt external interrupt 4 4 serial channel 0 interrupt external interrupt 5 5 C external interrupt 6 each group of interrupt sources can be programmed individually to one of four pr iority levels (as shown in table 33 ) by setting or clearing one bit in the sfr interrupt priority register ip0 ( sfr 0xa9 ) and one in downloaded from: http:///
71m6545/71M6545H data sheet 44 v2 ip1 (sfr 0xb9) ( table 34 ). if requests of the same priority level are received simultaneously, an inter nal polling sequence as shown in table 35 determines which request is serviced first. changing interrupt priorities while interrupts are enabled can easily cause soft ware defects. it is best to set the interrupt priority registers only once during initialization before interrupts are enabled. table 33 : interrupt priority levels ip1 [x] ip0 [x] priority level 0 0 level 0 (lowest) 0 1 level 1 1 0 level 2 1 1 level 3 (highest) table 34 : interrupt priority registers ( ip0 and ip1 ) register address bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) ip0 sfr 0xa9 C C ip0[5] ip0[4] ip0[3] ip0[2] ip0[1] ip0[0] ip1 sfr 0xb9 C C ip1[5] ip1[4] ip1[3] ip1[2] ip1[1] ip1[0] table 35 : interrupt polling sequence external interrupt 0 polling sequence serial channel 1 interrupt timer 0 interrupt external interrupt 2 external interrupt 1 external interrupt 3 timer 1 interrupt external interrupt 4 serial channel 0 interrupt external interrupt 5 external interrupt 6 interrupt sources and vectors table 36 shows the interrupts with their associated flags and vector addresses. table 36 : interrupt vectors interrupt request flag description interrupt vector address ie0 external interrupt 0 0x0003 tf0 timer 0 interrupt 0x000b ie1 external interrupt 1 0x0013 tf1 timer 1 interrupt 0x001b ri0/ti0 serial channel 0 interrupt 0x0023 ri1/ti1 serial channel 1 interrupt 0x0083 iex2 external interrupt 2 0x004b iex3 external interrupt 3 0x0053 iex4 external interrupt 4 0x005b iex5 external interrupt 5 0x0063 iex6 external interrupt 6 0x006b downloaded from: http:///
71m6545/71M6545H data sheet v2 45 figure 12 : interrupt structure downloaded from: http:///
71m6545/71M6545H data sheet 46 v2 2.5 on - chip resources 2.5.1 physical memory 2.5.1.1 flash memory the 71m6545/h includes 64 kb of on - chip flash memory. the flash memory primarily contains mpu and ce program code. it also contains images of the ce ram and i/o ram. on power - up, before enabling the ce, the mpu co pies these images to their respective locations. f lash space allocated for the ce program is limited to 4096 16 - bit words ( 8 kb). t he ce program must begin on a 1 - kb boundary of the flash address space. the ce_lctn[ 5 :0] ( i/o ram 0x2109[5:0] ) field defines which 1 - kb boundary contains the ce code. thus, the first ce instruction is located at 1024* ce_lctn[ 5 :0] . flash memory can be accessed by the mpu, the ce, and by the spi interface (r /w). table 37 : flash memory access acce ss by access type condition mpu r/w/e w/e only if ce is disabled. ce r spi r/w/e access only when sfm is invoked (mpu halted). flash write procedures if the flsh_unlock [3:0] (i/o ram 0x2702[7:4]) key is correctly programmed, the mpu may write to the flash memory. this is one of the non - volatile storage options available to the user in addition to external eeprom. the flash program write enable bit, flsh_pstwr (sfr 0xb2[0]), differentiates 80515 data store instructions (movx@dptr,a) between flash and xram writes. this bit is autom atically cleared by hardware after each byte write operation. write operations to this bit are inhibited when inter rupts are enabled. if the ce is enabled ( ce_e = 1 , i/o ram 0x2106[0] ), flash write operations must not be attempted unless flsh_ pstwr is set. this bit enables the posted flash write capability. flsh_ pstwr ha s no effect when ce_e = 0). when ce_e = 1, however, flsh_ pstwr delay s a flash write until the time interval between the ce code passes. during this delay time, the flsh_pend ( sfr 0xb2[3] ) bit is high, and the mpu continue s to execute commands. when the ce code pass ends (ce_busy falls), the flsh_pend bit fall s and the write operation occur s . the mpu can query the flsh_pend bit to determine when the write operation has been completed. while flsh_pend = 1, further flash write re quests are ignored. updating individual bytes in flash m emory the original state of a flash byte is 0xff (all b its are 1 ). once a value other than 0xff is written to a flash memory cell, over writing with a different value usually requires that the cell be erased first . since cells cannot be erased individually, the page has to be first copied to ram, followed by a page erase. after this, the page can be updated in ram and then written back to the flash memory. flash erase procedures flash erasure is initiated by writing a specific data pattern to speci fic sfr registers in the proper sequence. these special pattern/sequence requirements prevent inadvertent erasure of the flash mem ory. the mass erase sequence is: ? write 1 to the flsh_meen bit ( sfr 0xb2[1] ). ? write the pattern 0xaa to the flsh_erase ( sfr 0x94 ) register . the mass erase cycle can only be initiated when the ice port is enabled. downloaded from: http:///
71m6545/71M6545H data sheet v2 47 the page erase sequence is: ? write the page address to flsh_pgadr [6:0] ( sfr 0xb7[7:1] ) . ? write the pattern 0x55 to the flsh_erase register ( sfr 0x94 ). program security when enabled, the security feature limits the ice to global f lash erase operations only. all other ice operations , such as reading via the spi or ice port, are blocked. this guarantees the security of the users mpu and ce program code. security is enabled by mpu code that is execute d in a 64 ckmpu cycle pre - boot interval before the primary boot sequence begins. once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip reset. the first 64 cycles of the mpu boot code are called the pre - boot phase because during this phase the ice is inhibited. a read - only status bit, preboot (sfr 0xb2[7]) , identifies these cycles to the mpu. upon completion of pre - boot, the ice can be enabled and is permitted to take control of the mpu. t he security enable bit, secure (sfr 0xb2[6]) , is reset whenever the chip is reset. hardware associated with the bit allows only ones to be written to it. thus, pre - boot code may set secure to enable the security feature but may not reset it. once secure is set, the pre - boot and ce code are protected from e r asure, and no external read of program code is possible . specifically, when the secure bit is set , the following applies : ? the ice is limited to bulk flash erase only. ? page zero of flash memory, the preferred location for the users pre - boot code, may not be page - erased by either mpu or ice. page zero may only be erased with global fl ash erase. ? write operation s to page zero, whether by mpu or ice are inhibited. the 71m6545/h also includes hardware to protect against unintentional flash write and eras e. to enable flash write and erase operations, a 4 - bit hardware key that must be written to the flsh_unlock[3:0] field . the key is the binary number 0010. if flsh_unlock[3:0] is not 0010, the flash erase and write operation is inhibited by hardware. proper operation of this security key requir es that there be no firmware function that writes 0010 to flsh_unlock[3:0] . the key should be written by the external spi master, in the case o f spi flash programming (sfm mode), or through the ice interface in t he case of ice flash programming. when a boot loader is used, the key should be sent to the boot load code w hich then w rites it to flsh_unlock[3:0]. flsh_unlock[3:0] is not automatically reset. it should be cleared when the spi or ice has finished changing the flash. table 38 summarizes the i/o ram registers used for flash security. table 38 : flash security name location rst wk dir description flsh_unlock[3:0] 2702[7:4] 0 0 r/w must be a 2 to enable any flash modification. see the description of flash security for more details. secure sfr b2[6] 0 0 r/w inhibits erasure of page 0 and flash addresses above the beginning of ce code as defined by ce_lctn[5:0 ] (i/o ram 0x2109[5:0]) . also inhibits the read of flash via the ice and spi ports. spi flash mode in normal operation, the spi slave interface cannot read or write the flash m emory. however, the 71m6545/h contains a special flash mode (sfm) that facilitates initial (production) programming of the flash memory. when the 71m6545/h is in sfm mode, the spi interface can erase, read, and write the flash. other memory elements such as xram and i / o ram are not accessible to the spi in this mode. in order to protect the flash contents, several operations are required before th e sfm mode is successfully invoked. downloaded from: http:///
71m6545/71M6545H data sheet 48 v2 if the spi port is used for code updates (in lieu of a programmer that uses the ice port), then a code that disables the flash access via spi can potentially lock out flash program updates. details on the sfm ca n be fou nd in 2.5.12 spi slave port . 2.5.1.2 mpu/ce ram the 71m6545/h includes 5 kb of static ram memory on - chip (xram) plus 256 bytes of internal ram in the mpu core. the 5kb of static r am are used for data storage by both mpu and ce and f o r the com munica tion between mpu and ce . 2.5.1.3 i/o ram (configuration ram) the i/o ram can be seen as a series of hardware registers that control ba sic hardware functions. i/o ram address space starts at 0x2000. the registers of the i/o ram are listed in table 59 . the 71m6545/h includes 128 bytes non - volatile ram memory on - chip in the i/o ram address space (addresses 0x2800 to 0x287f). this memory section is supported by the v oltage applied at vbat_r tc , and the data in it are preserved in slp mode provided that the voltage at the vbat_rtc pin is within specification. 2.5.2 oscillator the 71m6545/h oscillator drives a standard 32.768 khz watch crystal . this type of crystal is accurate and do es not require a high - current oscillator circuit . the oscillator has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling ca pability. the oscillator p ower dissipation is very low to maxi mize the lifetime of any battery attached to vbat _rtc . oscillator calibration can improve the accuracy of both the rtc and metering. refer to 2.5.4 , real - time clock (rtc ) for more information. the oscillator is powered from the v3p3sys pin or from the vbat _rtc pin, depending on the v3ok in ternal bit (i.e., v3ok = 1 if v3p3sys 2.8 vdc and v3ok = 0 if v3p3sys < 2.8 vdc). the oscillator requires approximately 100 na, which is negligible compared to the internal leakage of a battery. if vbat_rtc is connected to a drained battery or disconnected, a battery tes t that sets temp_bat may drain the supply connected to vbat_rtc and cause the oscillator to stop. a stopped oscillator may force the device to reset. therefore, an unexpected reset during a battery test should be interpreted as a battery failure. 2.5.3 pll and internal clocks tim ing for the device is derived from the 32.768 khz crystal oscillator output that is multiplied by a pll by 600 to obtain 19.660800 mhz, the master clock (mck) . all o n- chip timing , except for the rtc clock, is derived from mck. table 39 provides a summary of the clock functions and their controls . the two general - purpose counter/timers contained in the mpu are controlled by ckmpu (see 2.4.8 timers and counters ). the master clock can be boosted to 19.66 mhz by setting the pll_fast bit = 1 ( i/o ram 0x2200[4] ) and can be reduced to 6.29 mhz by pll_fast = 0. the mpu clock frequency ckmpu is determined by another divider controlled by the i/o ram control field mpu_div [2:0] (i/o ram 0x2200[2:0]) and can be set to mck*2 -( mpu_div +2) where mpu_div [2:0] may vary from 0 to 4 . when the ice_e pin is high, t he cir cuit also generates the 9.8 3 mhz clock for use by the emul ator. when the part is waking up from slp mode, the pll is turn ed on in 6.29 mhz mode , and the pll frequency is not be accurate until the pll_ok ( sfr 0xf9[4] ) flag rises. due to potential overshoot, the mpu should not change the value of pll_fast until pll_ok i s tr ue . downloaded from: http:///
71m6545/71M6545H data sheet v2 49 table 39 : clock system summary clock derived from fixed frequency or range function pll_fast =1 pll_fast =0 controlled by osc crystal 32.768 khz C crystal clock mck crystal/pll 19.660800 mhz (600*ck32) 6.291456 mhz (192*ck32) pll_fast master clock ckce mck 4.9152 mhz 1.5728 mhz C ce clock ckadc mck 4.9152 mhz, 2.4576 mhz 1.572864 mhz, 0.786432 mhz adc_div adc clock ckmpu mck 4.9152 mhz 307.2 khz 1.572864 mhz 98.304 khz mpu_div [2:0] mpu clock ckice mck 9.8304 mhz 614.4 khz 3.145728 mhz 196.608 khz mpu_div[2:0] ice clock ckoptmod mck 38.40 khz 38.6 khz C optical uart modulation ck32 mck 32.768 khz C 32 khz clock 2.5.4 real - time clock (rtc) 2.5.4.1 rtc general description the rtc is driven directly by the crystal oscillator and is powered by either the v3p3sys pin or the vbat_rtc pin , depending on the v3ok internal bit . the rtc consists of a counter chain and output reg isters. the counter chain consists of registers for seconds, minutes , hours, day of week, day of month, month, and year. the chain registers are supported by a shadow register that facilitates read and write operations. table 40 shows the i/o ram registers for accessing the rtc. 2.5.4.2 accessing the rtc two bits, rtc_rd (i/o ram 0x2890[6] ) and rtc_wr (i/o ram 0x2890[7]) , control the behavior of the shadow register. when rtc_rd is low, the shadow register is updated by the rtc after each two milli seconds. when rtc_rd is high, this update is halted and the shadow register contents become stationary and are suitable to be read by the mpu. thus, when the mpu wishes to read the rtc, it freeze s the shadow register by setting the rtc_rd bit, read s the shadow register, and then lower s the rtc_rd bit to let updates to the shadow register resume. since the rtc clock is only 500 hz, there may be a delay of approximately 2 ms from when the rtc_rd bit is lowered until the shadow register receives its first update. r eads to rtc_rd continue s to return a one until the first shadow update occurs. when rtc_wr is high, the update of the shadow register is also inhibited. during t his time, the mpu may overwrite the contents of the shadow register. when rtc_wr is lowered, the shadow register is written into the rtc counter on the next 500hz rtc clock. a change bit is included f or each word in the shadow register to ensure that only programmed words are updated when the mpu writes a zero to rtc_wr . reads of rtc_wr return s one until the counter has actually been updated by the register. the sub - second register of the rtc, rtc_sbsc (i/o ram 0x2892) , can be read by the mpu after the one second interrupt and before reaching the next one second boundary. rtc_sbsc contai ns the count since the last full second , in 1/128 second nominal clock periods, until the next one - second boundary. when the rst_subsec bit is written, the subsec counter is restarted, counting from 0 to 127. reading and resetting the sub - second counter can be used as part of an algorithm to accurately set the rtc. the rtc is capable of processing leap years. each counter has its own output register. the rtc cha in registers are not be affected by the reset pin, watchdog timer resets, or by transitions b etween the slp mode and mission mode. downloaded from: http:///
71m6545/71M6545H data sheet 50 v2 table 40 : rtc control registers name location rst wk dir description rtca _adj[6:0] 2504 [6:0] 40 -- r/w register for analog rtc frequency adjust ment . rtc_p[16:14] rtc_p[13:6] rtc_p[5:0] 289b[2:0] 289c[7:0] 289d[7:2] 4 0 0 4 0 0 r/w registers for digital rtc adjust ment. 0x0ffbf rtc_p 0x10040 rtc_q[1:0] 289d[1:0] 0 0 r/w register for digital rtc adjustment. rtc_rd 2890[6] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu reads. when rtc_rd is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. rtc_wr 2890[7] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu write operation s. when rtc_wr is cleared, the contents of the shadow register are written to the rtc counter on the next rtc clock (~1 khz). when rtc_wr is read, it return s 1 as long as rtc_wr is set, and continue s to return one until the rtc counter is updated . rtc_fail 2890[4] 0 0 r indicates that a count error has occurred in the rtc and that the time is not trustworthy. this bit can be cleared by writing a 0 . rtc_sbsc[7:0] 2892[7:0] r time remaining since the last 1 second boundary. lsb = 1/128 second. 2.5.4.3 rtc rate control the 71m6545/h has two rate adjustment mechanisms: ? the first rate adjustment mechanism is an analog rate adjustment, using the i/o ram register rtca_adj[6:0] , that trims the crystal load capacitance. ? the second rate adjustment mechanism is a digital rate adjust that affect s the way the clock frequency is processed in the rtc. setting rtca_adj[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. setting rtca_adj[6:0] to 0x7 f maximizes the load capacitance, minimizing the oscillator frequency. the adjustable capacitance is approximately: pf adj rtca c adj 5.16 128 _ ? = the precise amount of adjustment depend s on the crystal properties, the pcb layout and the value of the external crystal capacitors. the adjustment may occur at any time, and t he resulting clock frequency should be measured over a one - second interval. the second rate adjustment is digital, and can be used to adjust the clock rate up to 988ppm, with a resolution of 3.8 ppm (1.9 ppm). the rate adjustment is implemented starting at the next second - boundary fol lowing the adjustment . since the lsb results in an adjustment every four seconds, the frequency should be measured over an interval that is a multiple of four seconds . the clock rate is adjusted by writing the appropriate values to rtc_p[ 16:0] ( i/o ram 0x289b[2:0], 0x289c, 0x289d[7:2] ) and rtc_q[1:0] (i/o ram 0x289d[1:0]) . updates to rtc rate adjust registers, rtc_p and rtc_q , are done through the shadow register described above. the new values are loaded into the counters when rtc_wr (i/o ram 0x2890[7] ) is lowered. the default frequency is 32,768 rtclk cycles per second. to shift the clock frequency by ? ppm, rtc_p and rtc_q are calculate d using the following equation: downloaded from: http:///
71m6545/71M6545H data sheet v2 51 ?? ? ?? ? + ?? + ? = + ? ? 5.0 10 1 8 32768 rtc_q rtc_p 4 6 floor conversely, the amount of ppm shift for a given value of 4rtc_p + rtc_q is: 6 10 1 4 8 32768 ) ( ? ? ?? ? ? ?? ? ? + ? ? = ? q p rtc rtc ppm for example, for a shift of - 988 ppm, 4 ? rtc_p + rtc_q = 262403 = 0x40103. rtc_p [16:0] = 0x10040, ( i/o ram 0x289b[2:0], 0x289c, 0x289d[7:2] ) and rtc_q [1:0] = 0x03 ( i/o ram 0x289d[1:0] . the default values of rtc_p [16:0] and rtc_q [1:0] , corresponding to zero adjustment, are 0x10000 and 0x0, respectivel y . two settings for the tmux2out test pi n , pulse_1s and pulse_4s, are available for measuring and calibrating the rtc clock frequency. these are waveforms of approxim ately 25% duty cycle with 1s or 4s period. default values for rtc a _adj [6:0] , r tc_p [16:0] and r tc_q [1:0] should be nominal values, at the center of the ad just ment range. uncalibrated extreme values (zero , for example) can cause incorrect operation. if the crystal temperature coefficient is known, the mpu can integrate tem perature and correct the rtc time as necessary. alternatively, the characteristics can be loaded int o an nv ram and the osc_comp ( i/o ram 0x28a0[5 ]) bit may be set. in this case, the oscillator is adjusted automatically, even in slp mode. see 2.5.4.4 rtc temperature compensation for details. 2.5.4.4 rtc temperature compensation t he 71m6545/h can be configured to regularly measure die temperature, including in slp mode , provided that the vbat_rtc pin is supplied with a voltage within specificati on provided by a battery . if enabled by osc_comp , this temperature inform ation is auto matically used to correct for the temperature variation of the crystal. a table lookup method is used . table 41 shows i/o ram registers in volved in automatic rtc temperature compensation. table 41 : i/o ram registers for rtc temperature compensation name location rst wk dir description osc_comp 28a0[5] 0 0 r/w enables the automatic update of rtc_p [16:0] and rtc_q [1:0] every time the temperature is measured. stemp[10:3] stemp[2:0] 2 881[7:0 ] 2 88 2 [7:5 ] C C r the re s ult of the temperature measure ment (10 - bits of magnitude data plus a sign bit) . lkpaddr[6:0] 2887[6:0] 0 0 r/w the address for reading and writing the rtc lookup ram. lkpautoi 2887[7] 0 0 r/w auto - increment flag. when set, lkpaddr [6:0] auto increment s every time lkp_rd or lkp_wr is pulsed. the incremented address can be read at lkpaddr [6:0] . lkpdat[7:0] 2888[7:0] 0 0 r/w the data for reading and writing the rtc lookup ram. lkp_rd lkp_wr 2889[1] 2889[0] 0 0 0 0 r/w r/w strobe bits for the rtc lookup ram read and write. when set, the lkpaddr [6:0] and lkpdat registers are used in a read or write operation. when a strobe is set, it stay s set until the operation completes, at which time the strobe is cleared and lkpaddr [6: 0] is incremented if lkpautoi is set. referring to figure 13 the table lookup method uses the 10 - bits plus sign - bit value in stemp [10:0] right - shifted by two bits to obtain an 8 - bit plus sign value (i.e., nv ram address = stemp [10:0] /4). a limiter ens ures that the resulting look - up address is in the 6 - bit plus sign range of - 64 to +63 (decimal). downloaded from: http:///
71m6545/71M6545H data sheet 52 v2 the 8 - bit nv ram content pointed to by the address is added as a 2s complement value to 0x40000, the nominal val ue of 4* rtc_p [16:0] + rtc_q [1:0] . refer to 2.5.4.3 rtc rate control for information on the rate adjustments performed by registers rtc_p [ 16:0] and rtc_q [ 1:0] . the 8 - bit values loaded in to nv ram must be scaled correctly to produce rate adjustments that are consistent with the equations given in 2.5.4.3 rtc rate control for rtc_p [16:0] and rtc_q [1:0] . note that the sum of the looked - up 8 - bit 2s complement value and 0x40000 form a 19 - bit value, which is equal to 4* rtc_p [16:0] + rtc_q [1:0] , as shown in figure 13 . the output of the temperature compensation is automatically loaded into the rtc_p[16:0] and rtc_q[1:0] locations after each look - up and summation operation. 0x40000 19 10+s stemp >>2 63 -64 -64 63 255 -256 limit look up ram addr 6+s 8+s q 7+s 4*rtc_p+rtc_q 19 figure 13 : automatic temperature compensation as mentioned above, the stemp [10:0] digital temperature values are scaled such that the corresponding nv ram addresses are equal to stemp [10:0] /4 (limited in the range of - 64 to +63) . see 2.5.5 71m6545/h temperature sensor on page 53 for the equations to calculate temperature in degrees c from the stemp[10:0] reading. for proper operation, the mpu has to load the lookup table with values that refle ct the crystal properti es with respect to temperature, which is typically done once during initiali zation. since the lookup table is not directly addressable, the mpu uses the following procedure to load the nv ram table: 1. set the lkpautoi bit ( i/o ram 0x2887[7] ) to enable address auto - increment . 2. write zero into the i/o ram register lkpaddr[6:0] ( i/o ram 0x2887[6:0] ). 3. write the 8 - bit dat um into i/o ram register lkpdat ( i/o ram 0x 2888 ). 4. set the lkp_wr bit ( i/o ram 0x2889[0 ] ) to write the 8 - bit datum into nv_ram 5. wait for lkp_wr to clear ( lkp_wr auto - clears when the data has been copied to nv ram) . 6. repeat steps 3 through 5 until all data has been written to nv ram. the nv ram table can also be read by writing a 1 into the lkp_rd bit ( i/o ram 0x2889[1] ). the process of reading f rom and writing to the nv ram is accelerated by setting the lkpautoi bit ( i/o ram 0x2887[7] ). when lkpautoi is set, lkpaddr[6:0] ( i/o ram 0x2887[6:0] ) auto - increment s every time lkp_rd or lkp_wr is pulsed. it is also possible to perform random access of the nv ram by writ ing a 0 to the lkpautoi bit and loading the desired address into lkpaddr[6:0] . if the oscillator temperature compensation feature is not being used, it i s possible to use the nv ram storag e area as ordinary battery - backed nv storage space using the procedure described above to read and write nv ram data. in this case, the osc_comp bit ( i/o ram 0x28a0[5] ) is reset to disable the automatic oscillator temperature compensation feature. 2.5.4.5 rtc interrupts the rtc generates interrupts each second and each minute. these interrupts ar e called rtc_1sec and rtc_1min . in addition, the rtc functions as an alarm clock by generating an interrupt when the mi nutes and hours register s both equal their resp ective target count s. the alarm clock interrupt is called rtc_ t. all three interrupts appear in the mpus external interrupt 6. see table 31 in the interrupt section for the enable bit s and flags for these interrupts. the minute and hour target registers are listed in table 42 . downloaded from: http:///
71m6545/71M6545H data sheet v2 53 tabl e 42 : i/o ram registers for rtc interrupts name location rst wk dir description rtc_tmin[5:0] 289e[5:0] 0 0 r/w the target minutes register. see below. rtc_thr[4:0] 289f[4:0] 0 0 r/w the target hours register. the rtc_ t interrupt occur s when rtc_min [5:0] becomes equal to rtc_tmin [5:0] and rtc_hr [4:0] becomes equal to rtc_thr [4:0] . 2.5.5 71m6545/h temperature sensor the 71m6545/h includes an on - chip temperature sensor for determining the temperature of its bandgap re ference . the primary use of the temperature data is to determine the magnitude of compensation re quired to offset the th ermal drift in the system for the com pensation of current, voltage and energy mea surement and the rtc . s ee 4.5 metrology temperature compensation on page 74 . also see 2.5.4.4 rtc temperature compensation on page 51 . the temperature sensor can be used to compensate for the frequency variation of the c rystal, during ac power outages, provided the vbat_rtc voltage is within specification (supplied by a battery) . see 2.5.4.4 rtc temperature compensation on page 51 . in msn mode, the temp erature sensor is awakened on command from the mpu by setting the temp_start (i/o ram 0x 28b4 [6]) control bit . during power outages and while operating from vbat_rtc power , it is awakened at a regular rate set by temp_per[2:0] (i/o ram 0x28a0[2:0]) . the result of the temperature measurement can be read from the two i/o ram locations stemp[10:3] ( i/o ram 0x2881) and stemp[2:0] (i/o ram 0x2882[7:5] ). note that both of these i/o ram locations must be read and properly combined to form the stemp[10:0] 11 - bit value (see stemp in table 43 ) . the resulting 11 - bit value is in 2s complement form and ranges from - 1024 to +1023 ( decimal ) . the equation s below are used to calculate the sensed temperature from the 11 - bit stemp[10:0] reading. for the 71m6545 in msn mode (with temp_pwr = 1): 22 325 .0 ) ( + ? = stemp c temp o for the temperature sensors in the 71M6545H : if stemp 0: ???? ( ) = 0. 325 ? ????? + 0. 00218 ? ?????? 2 ? 0. 609 ? ?????? + 64 .4 if stemp > 0: ???? ( ) = 63 ? ????? ???? _ 85 + 0. 00218 ? ?????? 2 ? 0. 609 ? ?????? + 64 .4 the t emp_85[10:0] trim fuses are read from the info page. see 5.3 reading the info page (71M6545H only) on page 98 for information on how to read the 71M6545H trim fuses. table 43 s hows the i/o ram registers used for temperature and battery measurement. i f temp_pwr selects vbat_rtc when the battery is nearly discharged, the temperature measurement may not finish. in this case, firmware may complete the measurement by selecting v3p3d ( temp_pwr = 1). downloaded from: http:///
71m6545/71M6545H data sheet 54 v2 table 43 : i/o ram registers for temperature and battery measurement name location rst wk dir description tbyte_busy 28a0[3] 0 0 r indicates that hardware is still writing the 0x28a0 byte. additional writes to this byte are locked out while it is one. write duration could be as long as 6 ms. temp_per[2:0] 28a0[2:0] 0 C r/w sets the period between temperature measurements . auto mat ic measurements can be enabled in any mode (msn and during ac power outages if the vbat_rtc voltage is within specification, as supplied by a battery ). temp_per time 0 manual updates (see temp_start ) 1-6 2 ^ (3+ temp_per ) (seconds) 7 continuous temp_bat 28a0[4] 0 C r/w causes the vbat _rtc pin to be measured whenever a temperature measurement is performed. temp_start 28b4[6] 0 C r/w temp_per[2:0] must be zero in order for temp_start to function. if temp_per[2:0] = 0, then setting temp_start s tarts a temperature measurement. this bit is i gnored in slp mode . hardware clears temp_start when the temperature measurement is complete. temp_pwr 28a0[ 6] 0 C r/w selects the power source for the temp erature sensor: 1 = v3p3d, 0 = vbat_r tc. this bit is ignored in slp mode , where the temperature sensor is always powered by vbat_rtc. reserved 28a0[7 ] 0 C r/w must always be zero. temp_test[1:0] 2500[1:0] 0 C r/w test bits for the temperature monitor vco. temp_test must be 00 in regular operation. any other value cause s the vco to run continuously with the control voltage described below. temp_test function 00 normal operation 01 reserved for factory test 1x reserved for factory test stemp[10:3] stemp[2:0] 2881[7:0] 2882[7:5] r r the result of the temperature measurement. the stemp[10:0] value may be obtained in c with a single 16 - bit read and divide by 32 operation as follows: volatile int16_t xdata stemp _at_0x2881; fa = (float)(stemp/32); bsense[7:0] 2885[7:0] C C r the result of the battery measurement. bcurr 2704[3] 0 0 r/w connects a 100 a load to the battery (vbat_rtc pin) . 2.5.6 71m6xx3 temperature sensor the 71m6xx3 includes an on - chip temperature sensor for determining the temperature of its bandgap re ference. the primary use of the temperature data is to determine the magnitude of compensation re quired to offset the thermal drift in the system for the com pensa tion of the current measurement performed by the71m6xx3. see the 71m6xxx data s heet for the equation to calculate temperature from the 71m6xx3 stemp[10:0] reading. also, s ee 4.5 metrology temperature compensation on page 74 . downloaded from: http:///
71m6545/71M6545H data sheet v2 55 see 2.2.8.3 control of the 71m6xx3 isolated sensor on page 22 for information on how to read the stemp[10:0] information from the 71m6xx3. 2.5.7 71m6545/h battery monitor the 71m6545/h temperature measurement circuit can also monitor the batter y at the vbat_rtc pin . when temp_bat ( i/o ram 0x28a0[4] ) is set, a battery measurement is performed as part of each temperature measurement. the value of the battery reading is stored in register bsense [7:0] (i/o ram 0x2885) . the following equations are used to calculate the voltage measured on the vba t_rtc pin from the bsense[7:0] and stemp[10:0] values. the result of the equation below is in volts. in msn mode, temp_pwr = 1 use: v stemp v bsense v rtc vbat 000297 .0 0246 .0) 142 ( 3.3 _ ? + ? ? + = in msn mode, a 100 a de - passivation load can be applied to the battery by setting the bcurr ( i/o ram 0x2704[3] ) bit. battery impedance can be measured by taking a battery measurement with and without bcurr . regardless of the bcurr bit setting , the battery load is never applied in slp mode. 2.5.8 71m6xx3 vcc monitor the 71m6xx3 monitor s its vcc pin voltage. the voltage of the vcc pin can be obtained by the 71m654 5/h by issuing a read command to the 71m6xx3. the 71m654 5/h must request both the vsense[7:0] and stemp[10:0] v alues from the 71m6xx3. see the 71m6xxx data sheet for the equation to calc ulate the 71m6xx3 vcc pin voltage from the vsense[7:0] and stemp[10:0] values read from the 71m6xx3. see 2.2.8.3 control of the 71m6xx3 isolated sensor on page 22 for information on how to read vsense[7:0] and stemp[10:0] from the 71m6xx3 remote sensors. 2.5.9 uart interface the 71m6545/h provides an asynchronous interface (uart) . the uart can be used to connect to amr modules, user interfaces, etc., and also support a mechanism for programming the on - chip flash memory. 2.5.10 dio pins on reset or power - up, all dio pins are dio inputs until they are configured for the desired co nfiguration under mpu control. after reset or power up, pins dio0 through dio1 4 are initially dio outputs, but are disabled by port_e = 0 (i/o ram 0x270c[5] ) to avoid unwanted pulses. after configuring pins dio0 through dio1 4 the host enables the pins by setting port_e = 1. dio pins can be configured independently as an input or output . for dio0 to dio1 4 , this is done with the sfr registers p0 (sfr 0x80) , p1 (sfr 0x90) , p2 (sfr 0xa0) and p3 (sfr 0xb0) as shown in table 44 . example: dio12 (pin 19 , gray fields in table 44 ) is configured as a dio output pin with a value of 1 (high) by w riting 1 to both p3[4]and p3[0] . table 44 : data/direction registers and internal resources for dio 0 to dio1 4 dio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pin # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dio data register 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 p0 (sfr80) p1 ( sfr9 0) p2 ( sfra 0) p3 ( sfrb 0) direction re gister : 0 = input, 1 = output 4 5 6 7 4 5 6 7 4 5 6 7 4 5 6 p0 (sfr80) p1 ( sfr9 0) p2 ( sfra 0) p3 ( sfrb 0) internal re sources configurable -- -- -- -- y y y y y y y y C C C the configuration for pins dio1 9 to dio 25, dio28 and dio29 are shown in table 45 the configuration for pins dio55 is shown in table 46 . downloaded from: http:///
71m6545/71M6545H data sheet 56 v2 table 45 : data/ direction registers for di o1 9- 25 and dio28 - 29 dio 19 20 21 22 23 24 25 28 29 pin # 14 13 12 11 10 9 8 7 6 dio data register 19 20 21 22 23 24 25 28 29 dio16[0 ] to dio31[0] (i/o ram 0x2420[0] to 0x242f[0]) direction re gister : 0 = input, 1 = output 19 20 21 22 23 24 25 28 29 dio 16[1] to dio 31[1] (i/o ram 0x2420[1] to 0x242f[1]) table 46 : data/direction registers for dio55 dio C C C C 55 C C C pin # C C C C 32 C C C dio data register C C C C 55 C C C dio 51[0] to dio 55[0] (i/o ram 0x2443[0] to 0x2447[0]) direction re gister: 0 = input, 1 = output C C C C 55 C C C dio 51[1] to dio 55[1] (i/o ram 0x2443[1] to 0x2447[1]) the pb pin is a dedicated digital input and is not part of the dio system. the ce features pulse counting registers and the ce pulse outputs are directly routed to the pulse interrupt input. thus, no routing of pulse signals to external pins is requir ed in order to generate pulse interrupts. a 3 - bit configuration word, i/o ram register dio_ rn [2:0] ( i /o ram 0x2009[2:0] through 0x200e[6:4] ) can be used for pins dio 2 through dio 11 (when configured as dio) and pb to indivi dually assign an internal resource such as an interrupt or a timer control ( dio_rpb [2:0], i/o ram 0x2450[2:0], configures the pb pin) . this way, dio pins can be tracked even if they are configured as outputs. table 47 lists the internal resources which can be as signed using dio_r 2 [2:0] (also called dio_rpb [2:0] ) through dio_r 11 [2:0] and dio_rpb [2:0] . if more than one input is connected to the same resource, the resources are combined using a logical or. table 47 : selectable resources using the dio_rn [2:0] bits value in dio_r n [2:0] resource selected for dio n or pb pin 0 none 1 reserved 2 t0 (counter0 clock) 3 t1 (counter1 clock) 4 hi gh priority i/o interrupt (int0 ) 5 low priority i/o interrupt (int1) when driving leds, relay coils etc., the dio pins should sink the current into gndd (as shown in figure 14 , right), not source it from v3p3d (as shown in figure 14 , left). this is du e to the resistance of the internal switch that connects v3p3d to v3p3sys . sourcing current in or out of dio pins other than those dedicated for wake func tions, for example with pull - up or pull - down resistors, should be avoided. violating this rule lead s to increased quiescent current from a battery connected to the vbat_rtc pin during slp mode . downloaded from: http:///
71m6545/71M6545H data sheet v2 57 v3p3sys v3p3d dio gndd mission sleep low high high-z v3p3sys v3p3d dio gndd mission sleep low high high-z not recommended recommended figure 14 : connecting an external load to dio pins 2.5.11 eeprom interface the 71m6545/h provides hardware suppor t for either a two - pin or a three - wire ( - wire) type of eeprom interfa ce. the interfaces use the eectrl (sfr 0x9f) and eedata (sfr 0x9e) registers for communication . two -p in eeprom interface the dedicated 2 - pin serial interface communicates with external eeprom devices . the interface is mul tiplexed onto the dio 2 ( sdck ) and dio 3 ( sdata ) pins and is selected by setting dio_eex [1:0] = 01 ( i/o ram 0x2456[7:6] ). the mpu communicates with the interface through the sfr registers eedata and eectrl . if the mpu wishes to write a byte of data to the eeprom, it places the data in eedata and then writes the transmit code to eectrl . this initiates the transmit operation which is finished when the busy bit falls . int5 is also asserted when busy falls . th e mpu can then check the rx_ack bit to see if the eeprom acknowledged the trans mission. a byte is read by writing the receive command to eectrl and waiting for the busy bit to fall . upon completion, the received data is in eedata . the serial transmit and receive clock is 78 khz during each transmission, and then holds in a high state until the next transmission . the eectrl bits when the two - pin interface is selected are shown in table 48 . table 48 : eectrl bits for 2 - pin interface status bit name read/ write reset state polarity description 7 error r 0 positive 1 when an illegal command is received. 6 busy r 0 positive 1 when serial data bus is busy. 5 rx_ack r 1 positive 1 indicates t hat the eeprom sent an ack bit. 4 tx_ack r 1 positive 1 indicates when an ack bit has been sent to the eeprom . 3:0 cmd[3:0] w 0000 positive cmd[3:0] operation 0000 no - op command. stops the i 2 c clock ( sdck ). if not issued, sdck keeps toggling. 0010 receive a byte from the eeprom and send ack. 0011 transmit a byte to the eeprom. 0101 issue a stop sequence. downloaded from: http:///
71m6545/71M6545H data sheet 58 v2 status bit name read/ write reset state polarity description 0110 receive the last byte from the eeprom and do not send ack. 1001 issue a start sequence. others no operation, set the error bit. the eeprom interface can also be operated by controlling the dio 2 and dio 3 pins directly. the direction of the dio line can be changed from input to output and an output value can be written with a single write operation, thus avoiding collisions (see table 14 port registers (dio0 - 14) ). therefore, no resistor is required in series sdata to protect against collisions. three-w ire ( - wire) eeprom interface with single data pin a 500 khz three - wire interface, using sdata, sdck , and a dio pin for cs is available . the interface is selected by setting dio_eex [1:0] = 10 . the eectrl bits when the three - wire interface is selected are shown in table 49 . when eectrl is written, up to 8 bits from eedata are either written to the eeprom or read from the eeprom, depending on the values of the eectrl bits. three-w ire ( - wire/spi ) eeprom interface with separate di/do pins if dio_eex[1:0] = 11 , the 71m6545/h three - wire interface is the same as above, except di and do are separate pins. in this case, dio 3 becomes do and dio 8 becomes di. the timing diagrams are the same as for dio_eex [1:0] = 10 except that all output data appears on do and all input data is expected on di. in this mode, di is ignored while data is being received on do. this m ode is compatible with spi modes 0,0 and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on the rising edge of the clock. table 49 : eectrl bits for the 3 -w ire interface control bit name read/ write description 7 wfr w wait for ready . if this bit is set, the trailing edge of busy is delayed until a rising edge is seen on the data line . this bit can be used during the last byte of a write command to cause the int5 interrupt to occur when the eeprom has finished its internal write sequence . this bit is ignored if hiz=0. 6 busy r asserted while the serial data bus is busy . when the busy bit falls, an int5 interrupt occurs. 5 hiz w indicates that the sd signal is to be floated to high impedance immed i ately after the last sdck rising edge. 4 rd w indicates that eedata ( sfr 0x9e ) is to be filled with data from eeprom. 3 :0 cnt[3:0] w specifies the number of clocks to be issued . allowed values are 0 through 8 . if rd = 1, cnt bits of data are read msb first, and right justified into the low order bits of eedata . if rd = 0, cnt bits are sent msb first to the eeprom, shifted out of the msb of eedata . if cnt[3:0] is zero, sdata simply obey s the hiz bit. the timing diagrams in figure 15 through figure 19 describe the 3 - wire eeprom interface behavior . all command s begin when the eectrl register is written. transactions start by first raising the dio pin that is connected to cs . multiple 8 - bit or less commands such as those shown in figure 15 through figure 19 are then sent via eectrl and eedata . when the transaction is finished, cs must be lowered . at the end of a read transaction, the eeprom driv es sdata, but transition s to hiz (high impedance) when cs falls . the firmware should then immediately issue a write command with cnt=0 and hiz=0 to take control of sdata and force it to a low - z state. downloaded from: http:///
71m6545/71M6545H data sheet v2 59 figure 15 : 3 -w ire interface . write command, hiz=0. figure 16 : 3 -w ire interface . write command, hiz=1 figure 17 : 3 -w ire interface . read command. figure 18 : 3 - wire interface . write command when cnt=0 figure 19 : 3 -w ire interface . write command when hiz=1 and wfr=1. sclk (output) busy (bit) cnt cycles (6 shown) sdata (output) write -- no hiz d2 d3 d4 d5 d6 d7 eectrl byte written int5 sdata output z (loz) cnt cycles (6 shown) write -- with hiz int5 eectrl byte written sclk (output) busy (bit) sdata (output) d2 d3 d4 d5 d6 d7 (hiz) (loz) sdata output z cnt cycles (8 shown) read d0 d1 d2 d3 d4 d5 int5 d6 d7 eectrl byte written sclk (output) busy (bit) sdata (input) sdata output z (hiz) cnt cycles (0 shown) write -- no hiz d7 int5 not issued cnt cycles (0 shown) write -- hiz int5 not issued eectrl byte written eectrl byte written sclk (output) busy (bit) sdata (output) sclk (output) busy (bit) sdata (output) (hiz) sdata output z sdata output z (loz) cnt cycles (6 shown) write -- with hiz and wfr eectrl byte written sclk (output) busy (bit) sdata (out/in) d2 d3 d4 d5 d6 d7 busy ready (from eeprom) int5 (from 6520) sdata output z (hiz) (loz) downloaded from: http:///
71m6545/71M6545H data sheet 60 v2 2.5.12 spi slave port the slave spi port communicates directly with the mpu data bus and is abl e to read and write data ram and configuration ram (i/o ram) locations . it is also able to send commands to the mpu. the interface to the slave port consists of the sp i_csz, sp i_c ki , s pi_ di and sp i_ do pins . additionally, the spi interface allows flash memory to be read and to be programm ed. to facilitate flash programming, cycling power or asserting reset c auses the spi port pins to default to spi mode. the spi port is disabled by clearing the spi_e bit (i/o ram 0x270c[4]) . possible applications for the spi interface are: 1) an external host reads data from ce locations to obtain metering informati on. this can be used in applications where the 71m6545/h function as a smart front - end with preprocessing capability. since the addresses are in 16 - bit format , any type of xram data can be accessed: ce, mpu, i/o ram, but not sfrs or the 80515 - internal register bank. 2) a communication link can be established via the spi interface: by writing into mpu memory locations, the external host can initiate and control processes in the 71m6545/h mpu. w riting to a ce or mpu location normally generates an interrupt, a function that can be used to si gnal to the mpu that the byte that had just been written by the external host must be read and processed. data can also be inserted by the external host without generating an interrupt. 3) an external dsp can access front - end data generated by the adc. this mode of operation uses the 71m6545/h as an analog front - end (afe). 4) flash programming by the external host (spi flash mode) . spi transactions a typical spi transaction is as follows. while spi_csz is high, t he port is held in an initialized/reset state. during this state, spi_do is held in high impedance state and all transitions on spi_clk and spi_di are ignored. when spi_csz falls, the port begin s the transaction on the first rising edge of spi_clk. as shown in table 50 , a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status byte, followed by one or more bytes of data. the transaction ends when spi_csz is raised. som e transactions may consist of a command only. when spi_csz rises, spi command bytes that are not of the form x000000 0 cause the spi_cmd ( sfr 0xfd ) register to be updated and then cause an interrupt to be is sued to the mpu. the exception is if the transaction was a single byte. in this case, the spi_cmd byte is always updated and the interrupt issued. spi_cmd is not cleared when spi_csz is high. the spi port supports data transfers up to 10 mb/s. a serial read or write operation requires at least 8 clocks per byte, guaranteeing spi access to the ram is no faster than 1.25 mhz, thus ensuring that spi access to dram is always possible. downloaded from: http:///
71m6545/71M6545H data sheet v2 61 table 50 : spi transaction fields field name required size (bytes) description address yes, except single byte transaction 2 16 - bit address. the address field is not required if the transaction is a simple spi command . command yes 1 8- bit command . this byte can be used as a command to the mpu. in multi - byte transactions, the msb is the r/w bit. unless the transaction is multi - byte and spi_ cmd is exactly 0x80 or 0x00, the spi_cmd register is updated and an spi interrupt is issued. otherwise, the spi_cmd register is unchanged and the interrupt is not issued. s tatus yes, if transaction includes data 1 8- bit status field, indicating the status of the previous transaction. this byte is also available in the mpu memory map as spi_stat (i/o ram 0x2708) . see table 52 for the contents. d ata yes, if transaction includes data 1 or more the read or write data. address is auto incremented for each new b yte. the spi_stat byte is output on every spi transaction and indicates the parity of the previ ous transaction and the error status of the previous transaction. potential error s ources are: ? 71m6545/h not ready ? t ransaction not ending on a byte boundary. spi safe mode sometimes it is desirable to prevent the spi interface from writing to ar bitrary ram locations and thus disturbing mpu and ce operation. this is especially true in afe applicati ons. for this reason, the spi safe mode wa s created. in spi safe mode, spi write operation s are disabled except for a 16 byte transfer region at address 0x 400 to 0x 40f. if the spi host needs to write to other addresses, it must use the spi_cmd register to request the write operation from the mpu . spi safe mode is enabled by t he spi_safe bit (i/o ram 0x270c[3]) . single - byte transaction if a transaction is a single byte, the byte is interpreted as sp i_cmd. regardless of the byte value, single - byte transactions always update the spi_cmd register and cause an spi interrupt to be generated. multi - byte transaction as shown in figure 20 , multi - byte operations consist of a 16 bit address field, an 8 bit cmd, a status byte, and a sequence of data bytes. a multi byte transaction is three or more byte s. a15 a14 a1 a0 c0 0 31 x d6 d1 d0 d7 d6 d1 d0 c5 c6 c7 (from host) spi_csz (from host) spi_ck (from host) spi_di (from 6543) spi_do 8 bit cmd 16 bit address data[addr] data[addr+1] 15 16 23 24 32 39 extended read . . . serial read a15 a14 a1 a0 c0 c5 c6 c7 x 8 bit cmd 16 bit address data[addr] data[addr+1] extended write . . . serial write d6 d1 d0 d7 d6 d1 d0 x hi z hi z status byte st7 st6 st5 st0 d7 40 47 0 31 15 16 23 24 32 39 40 47 status byte d7 st7 st6 st5 st0 (from host) spi_csz (from host) spi_ck (from host) spi_di (from 6543) spi_do figure 20 : spi slave port - typical multi - byte r ead and w rite operations downloaded from: http:///
71m6545/71M6545H data sheet 62 v2 table 51 : spi c ommand sequences c ommand sequence description addr 1xxx xxxx status byte0 ... byten read data starting at addr. addr is auto - increment ed until spi_csz is raised. upon completion, spi_cmd ( sfr 0xfd ) is updated to 1xxx xxxx and an spi interrupt is generated. the exception is if the com mand byte is 1000 0000. in this case, no mpu interrupt is generated and spi_cmd is not updated. addr 0xxx xxxx status byte0 ... byten write data starting at addr. addr is auto - increment ed until spi_csz is raised. upon completion, spi_cmd is updated to 0xxx xxxx and an spi interrupt is generated. the exception is if the command byte is 0000 0000. in this case, no mpu interrupt is generated and spi_cmd is not updated. ta ble 52 : spi registers name location rst wk dir description ex_spi 2701[7] 0 0 r/w spi interrupt enable bit. spi_cmd sfr fd[7:0] C C r spi command. the 8 - bit command from the bus master. spi_e 270c[4] 1 1 r/w spi port enable bit. it enables the spi interface on pins spi_di, spi_do, spi_csz and spi_cki . ie_spi sfr f8[7] 0 0 r/w spi interrupt flag. set by hardware, cleared by writing a 0. spi_safe 270c[3] 0 0 r/w limits spi writes to spi_cmd and a 16 byte region in dram when set. no other write operations are permitted. spi_stat 2708[7:0] 0 0 r spi_stat contains the status results from the previous spi transaction bit 7 - 71m6545/h ready error: the 71m6545/h was not ready to read or write as directed by the previous command. bit 6 - read data parity: this bit is the parity of all bytes read from the 71m6545/h in the previous command. does not include the spi_stat byte. bit 5 - write data par ity: this bit i s the overall parity of the bytes written to the 71m6545/h in the previous command. i t includes cmd and addr bytes. bit 4 :2 - bottom 3 bits of the byte count. does not in clude addr and cmd bytes. one, two, and three byte instructions return 111. bit 1 - spi flash mode: this bit is zero when the test pin is zero. bit 0 - spi flash mode ready: used in spi flash mode. indicates that the flash is ready to receive another write instruction. spi flash mode (sfm) in normal operation, the spi slave interface cannot read or write the flash m emory. however, the 71m6545/h supports a special flash mode (sfm) which facilitates initial programming o f the flash memory. when the 71m6545/h is in this mode, the spi can erase, read, and write the flash memory . other memory elements such as xram and io ram are not accessible in this mode. in order to protect the flash contents, several operations are required before the sfm mode is success fully invoked. in sfm mode, the 71m6545/h supports n byte reads and du al - byte writes to flash memory . see the spi transaction description on page 60 for the format of read and write commands. since the flash writ e downloaded from: http:///
71m6545/71M6545H data sheet v2 63 op eration is always based on a two - byte word, the initial address must always be even. data is written to the 16 - bit flas h memory bus after the odd word is written. in sfm mode, the mpu is completely halted. for this reason, the interrupt feature described in the spi transaction section above is not available in sfm mode. the 71m6545/h must be reset by the wd timer or by t he reset pin in order to exit sfm mode. invoking sfm the following conditions must be met prior to invoking sfm: ? ice_e = 1. this disables the watchdog and adds another layer of protection against inadve rtent flash corruption. ? the external power source (v3p3sys, v3p3a) is at the proper level (> 3.0 vdc) . ? preboot = 0 ( sfr 0xb2[7]) . this validates the state of the secure bit (sfr 0xb2[6]) . ? secure = 0. this i/o ram register indicates that spi secure mode is not enabled. operations are limited to sfm mass erase mode if the secure bit = 1 (flash read back is not allowed in secure mode). ? flsh_unlock[3:0] = 0010 ( i/o ram 0x2702[7:4]) . the i/o ram r egisters sfmm ( i/o ram 0x2080 ) and sfms (i/o ram 0x2081) a re used to invoke sfm. only the spi interface has access to these two registers. this eliminates an indire ct path from the mpu for disabling the watchdog. sfmm and sfms need to be written to in sequence in order to invoke sfm. this sequential write process prevent s inadvertent entering of sfm. the sequence for invoking sfm is: ? first, write to sfmm ( i/o ram 0x2080 ) register . th e value written to this register defines the sfm mode. o 0xd1: mass erase mode. a flash mass erase cycle is invoked upon entering sfm. o 0x2e: flash read back mode. sfm is entered for flash read back purposes. flash writes are blocked and it is up to the user to guarantee that only previously unwritten loc ations are written. this mode is not accessible when spi secure mode is set. o sfm is not invoked if any other pattern is written to th e sfmm register. ? next, write 0x 96 to the sfms ( i/o ram 0x2081 ) register . this write invoke s sfm provided that the previous write operation to sfmm met the requirements. writing any other pattern to this register does not invoke sfm. addi tionally, any write operations to this register automatically reset t he previously written sfmm register values to zero. sfm d etails the following occur s upon entering sfm. ? the ce is disabled. ? the mpu is halted. once the mpu is halted it can only be restarted with a reset. this reset can be accomplished with the reset pin , a watchdog reset, or by cycling power . ? the flash control logic is reset in case the mpu was in the middle of a flash write operation or erase cycle. ? mass erase is invoked if specified in the sfmm ( i/o ram 0x2080 ) register (see invoking sfm, above) . the secure bit ( sfr 0xb2[6] ) is cleared at the end of this and all mass erase cycles. ? all spi read and write operation s now refer to flash instead of xram space. the spi host can access the current state of the pending multi - cycle flash access by performing a 4 - byte spi write of any ad dress and checking the status field. all spi write operations in sfm mode must be 6 - byte write transaction s that write two bytes to an even address. the write transactions must contain a command byte of 0x00 which i s the form that does not create an mpu interrupt. auto incrementing is disabled for write operation s. spi read transactions can make use of auto increment and may access single bytes. the command byte must always be 0x80 in sfm read transactions. downloaded from: http:///
71m6545/71M6545H data sheet 64 v2 spi commands in sfm interrupts are not generated in sfm since the mpu is halted . the format of the commands is shown in the spi transactions description. 2.5.13 hardware watchdog timer an independent, robust, fixed-duration, watchdog timer (wdt) i s included in the 71m6545/h. it uses the rtc crystal oscillator as its time base and must be refreshed by the mpu firmware at least every 1.5 seconds. when not refreshed on time, the wdt overflows and the p art is reset as if the reset pin were pulled high, except that the i/o ram bits are in the same state as af ter a wake-up from slp mode (see the i/o ram description in 5.2 for a list of i/o ram bit states after reset and wake-up). four thousand, one hundred ck32 cycles (or 125 ms) after th e wdt overflow, the mpu is launched from program address 0x0000. the watchdog timer is also reset when the internal signal wake= 0. the wdt is disabled when the ice_e pin is pulled high. 2.5.14 test ports (tmuxout and tmux2out pins) two independent multiplexers allow the selection of internal a nalog and digital signals for the tmuxout and tmux2out pins. one of the digital or analog signals listed in table 53 can be selected to be output on the tmuxout pin. the function of the multiplexer is controlled with the i/o ram regis ter tmux[4:0] (i/o ram 0x2502[4:0] , as shown in table 53 . one of the digital or analog signals listed in table 54 can be selected to be output on the tmux2out pin. the function of the multiplexer is controlled with the i/o r am register tmux2[4:0] (i/o ram 0x2503[4:0]) , as shown in table 54. the tmux and tmux2 i/o ram locations are non-volatile and their con tents are preserved by battery power and across resets. the tmuxout and tmux2out pins may be used for diagnosis purpose s or in production test. the rtc 1-second output may be used to calibrate the crystal oscillato r. the rtc 4-second output provides even higher precision. table 53: tmux[4:0] selections tmux[5:0] signal name description 1 rtclk 32.768 khz clock waveform 9 wd_rst indicates when the mpu has reset the watchdog timer . can be monitored to determine spare time in the watchdog t imer. a ckmpu mpu clock ? see table 8 d v3aok bit indicates that the v3p3a pin voltage is 3.0 v. the v3p3a and v3p3sys pins are expected to be tied together at th e pcb level. the 71m6545/h monitors the v3p3a pin voltage only. e v3ok bit indicates that the v3p3a pin voltage is 2.8 v. the v3p3a and v3p3sys pins are expected to be tied together at th e pcb level. the 71m654 monitors the v3p3a pin voltage only. 1b mux_sync internal multiplexer frame sync signal. see figure 4 and figure 5 . 1c ce_busy interrupt see 2.3.3 on page 25 and figure 12 on page 45 1d ce_xfer interrupt 1f rtm output from ce see 2.3.5 on page 26 note: all tmux[5:0] values which are not shown are reserved. downloaded from: http:///
71m6545/71M6545H data sheet v2 65 table 54 : tmux2[4 :0] selections tmux2[4:0] signal name description 0 wd_ovf indicates when the watchdog timer has expired (overflowed). 1 pulse_1s one second pulse with 25% duty cycle. this signal can be used to measure the deviation of the rtc from an ideal 1 second interval. multiple cycles should be averaged together to filter out jitter. 2 pulse_4s four second pulse with 25% duty cycle. this signal can be used to measure the deviation of the rtc from an ideal 4 second interval. multiple cycles should be averaged together to filter out jitter. the 4 second pulse provides a more precise measurement than the 1 second pulse. 3 rtclk 32.768 khz clock waveform 8 spare[1] bit C i/o ram 0x2704[1] copies the value of the bit stored in 0x2704[1]. for general purpose use. 9 spare[2] bit C i/o ram 0x2704[2] copies the value of the bit stored in 0x2704[2]. for general purpose use. a wake indicates when a wake event has occurred. b mux_sync internal multiplexer frame sync signal. see figure 4 and figure 5 . c mck see 2.5.3 on page 48 . e gndd digital gnd. use this signal to make the tmux2out pin static. 12 int0 C dig i/o interrupt 0. see 2.4.8 on page 38 . also see figure 12 on page 45 . 13 int1 C dig i/o 14 int2 C ce_pulse 15 int3 C ce_busy 16 int4 - vstat 17 int5 C eeprom/spi 18 int6 C xfer, rtc 1f rtm_ck (flash) see 2.3.5 on page 26 . note: all tmux 2[4 :0] values which are not shown are reserved. downloaded from: http:///
71m6545/71M6545H data sheet 66 v2 3 f unctional d escription 3.1 theory of operation the energy delivered by a power source into a load can be expressed as: = t dt tit v e 0 )( )( assuming phase angles are constant, the following formulae apply: ? p = real energy [wh] = v * a * cos * t ? q = reactive energy [varh] = v * a * sin * t ? s = apparent energy [vah] = 2 2 q p + for a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic con tent may change constantly . thus, simple rms measurements are inherently inaccurate . a modern solid - state electricity meter ic such as the 71m6545/h functions by emulating the integral oper ation above, i.e. it processes current and voltage samples through an adc at a cons tant frequency . as long as the adc resolution is high enough and the sample frequency is beyond the harmonic rang e of interest, the current and voltage samples, multiplied with the time period of sampling yield s an accurate quantity for the momentary energy . summing - up the momentary energy quantities over time result s in accumulated energy. figure 21 : voltage , current, momentary and accumulated energy figure 21 shows the shapes of v(t), i(t), the momentary power and the accumulated power , resulting from 50 samples of the voltage and current signals over a period of 20 ms . the application of 240 vac and 100 a results in an accumulation of 480 ws (= 0.133 wh) over the 20 ms period, as indicated by the a ccumulated p ower curve . the described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. 3.2 slp mode (sleep mode) shortly after system power (v3p3sys) is applied, the part will be in mi ssion mode (msn mode). msn mode means that the part is operating with system power and that the internal p ll is stable. this mode is the normal operation mode where the part is capable of measuring energy. -500 -400 -300 -200 -100 0 100 200 300 400 500 0 5 10 15 20 current [a] voltage [v] energy per interval [ws] accumulated energy [ws] downloaded from: http:///
71m6545/71M6545H data sheet v2 67 when system power is not available, the 71m6545 /h will be in slp mode, if a battery is attached to the vbat_rtc pin. shortly after system power is removed (v3p3sys < 3.0 vdc), vstat[2:0] will assume the value 001, issuing a warning to the mpu. the ic can still operate in this state, howev er, the analog functions are not con sidered accurate. assuming that the recommended mpu setup code is resid ent in flash memory (see 2.4.1 mpu setup code on page 30 ), at v3p3sys < 2.8 vdc, the 71m6545 /h will be forced to slp mode by the mpu setting the sleep bit ( i/o ram 0x28b2[7] ) . when system power is restored, the 71m6545 /h will automatically transition from slp mode back to msn mode. table 55 : available circuit functions circuit function system power battery power msn slp ce yes -- fir yes -- adc, vref yes -- pll yes battery m easurement yes t emperature sensor yes yes maximum mpu clock rate 4.92mhz (from pll) -- mpu_div clock divider yes -- ice yes -- dio pins yes -- watchdog timer yes -- v3p3d pin yes -- vdd pin yes -- eeprom interface (2 - wire) yes -- eeprom interface (3 - wire) yes -- uart (full speed) yes -- spi slave port yes -- spi special flash mode yes -- optical tx modulation yes -- flash read yes -- flash page erase yes -- flash write yes -- ram read and write yes -- osc and rtc yes yes ram data preservation yes -- nv ram data preservation yes yes C indicates not active the slp mode may be commanded by the mpu whenever main system power is absent by asserting the sleep bit . the purpose of the slp mode is to consume the least power while still maintainin g the rtc, temperature compensation of the rtc, and the non - volatile portions of the i/o ram. in slp mode, the v3p3d pin is disconnected, removing all sources of leakage from v3p3sys. the non - volatile memory domain and the basic functions, such as temperature sensor, oscillator, and rtc, are powered by the vbat_rtc input. in this mode, the i/o configuration bits and nv ram values are preserved and rtc and oscillator continue to run. this mode can be exited only by system power up . if the sleep bit is asserted when system power is present, the 71m6545 /h will still enter slp mode. it will drop wake, and then will begin the standard wake from sleep procedure. after the transition from slp mode to msn mode the pc will be at 0x0000, the xram is in an undefined state, and the i/o ram is only partially preserved (see the description of i/o ram states in 5.2 ). the non - volatile sec tions of the i/o ram are preserved unless reset goes high. downloaded from: http:///
71m6545/71M6545H data sheet 68 v2 the 71m6545/h features a temperature sensor and automatic digital temperature compens ation circuitry that can operate from a battery connected to the vbat_rtc pin, in the event of ac power loss. when ac power loss occurs, the 71m6545/h crystal oscillator, temperature sensor and di gital temperature compensation circuitry automatically obtain power from the vbat_rtc pin. see 2.5.4 real - time clock (rtc) on page 49 . 3.3 fault and reset behavior 3.3.1 events at power - down power fault detection is performed by internal comparators that monitor the vol tage at the v3p3a pin and also monitor the internally generated vdd pin voltage (2.5 vdc). the v3p3sys and v3p3a pins must be tied together at the pcb level, so that the comparators, which are internally con nected onl y to the v3p3a pin, are able to simultaneously monitor the common v3p3sys and v3p3a pin voltage. t he following discussion assumes that the v3p3a and v3p3sys pins are tied together at the pc b level. during a power fail ure, as v3p3a falls, two thresholds are detected: ? the first threshold, at 3 .0 vdc ( vstat[2:0] = 001 , sfr 0xf9[2:0] ) , warns the mpu that the analog modules are no longer accurate. other than warning the mpu, the hardware tak es no action when this threshold is crossed. this comparison produces an internal bit named v3oka . ? the second threshold, at 2.8 vdc , cause s the 71m6545/h to switch to battery power. this switching happen s while the flash and ram systems are still able to read and write. this comparison produces an internal bit named v3ok . the power quality is reflected by the vstat[2:0] register in i/o ram space, as shown in table 56 . the vstat[2:0] register is located at sfr address f9 and occupies bits 2 : 0. the vstat[2:0] field can only be read. in addition to the state of the main power, the vstat[2:0] register provide s information about the internal vdd voltage under battery power. note that if system power (v3p3a) is above 2.8 vdc , the 71m6545/h always switch es from battery to system power. table 56 : vstat[2:0] (sfr 0xf9[2:0]) vstat[2:0] description 000 system power ok. v3p3a > 3.0 vdc . analog modules are functional and accurate. 001 system power is low. 2.8 vdc < v3p3a < 3.0 vdc . analog modules not accurate. 010 vdd is ok. vdd > 2.25 vdc . the ic has f ull digital functionality. 011 2.25 vdc > vdd > 2.0 vdc . flash write operation s are inhibited. 101 vdd < 2.0, which means that the mpu is nearly out of vol tage. a reset occur s in 4 cycles of the crystal clock ck32 . the response to a system power fault is almost entirely controlled by f irmware. during a power failure, system power slowly fall s . an interrupt notifies the mpu whenever vstat[2:0] changes. i t is the mpus responsibility to reduce power, when necessary, by slowing the clock rate, disabling the pll, etc. precision analog components such as the bandgap reference, the bandgap buffer, and the adc are powered only by the v3p3a pin and become inaccurate and ultimately unavailable as the v3p3a pin voltage continues to drop (i.e., circuits powered by the v3p3a pi n are not backed by the vbat _rtc pin) . when the v3p3a pin falls below 2.8 vdc, the adc clocks are halted and the am plifiers are unbiased . meanwhile, control bits such as adc_e bit (i/o ram 0x2704[4]) are not affected, since their i/o ram storage is powered from the vdd pin (2.5 vdc). the vdd pin is suppl ied with power through an internal 2.5 vdc regulator that is connected to the v3p3d pin. note that the v3p3s ys and v3p3a pins are typically tied together at the pcb level. 3.3.2 reset sequence when the reset pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator and rtc . additionally, all i / o ram bits are forced to their rst state. a r eliable reset does not occur unti l downloaded from: http:///
71m6545/71M6545H data sheet v2 69 reset has been high at least for 2 s. note that tmux and the rtc are not reset unless the test pin is pulled high while reset is high . the reset control bit ( i/o ram 0x 2200[3] ) performs an identical reset to the reset pin except that a significantl y shorter reset timer is used. once initiated, the reset sequence wait s until the reset timer times out. the time out occur s in 4100 ce32 cycles (125 ms) , at which time the mpu begin s executing its pre - boot and boot sequences from address 0x0000. see 2.5.1.1 for a detailed description of the pre - boot and boot sequences . a softer form of reset is initiated when the e_rst pin of the ice interface is pulled low . this event causes the mpu and other regis ters in the mpu core to be reset but does not reset the remainder of the 71m6545/h . it does not trigger the reset sequence. this type of reset is intended to reset the mpu program, but not to make other changes to the chips state. 3.4 data flow and h ost communication the data flow between the compute engine (ce) and the host is shown in figure 22 . in a typical application, the 32 - bit ce se quen tially processes the samples from the voltage inputs on pins iadc0 - iadc1, vadc8 (va), iadc2 - iadc3, etc., performing calculations to measure active power (wh), reactive power (varh), a 2 h, and v 2 h for four - quadrant metering. these measurements are then accessed by the host via the spi interface, processed further and stored and/or displayed. for example, to obtain the rms current value in phase a, the host reads the i0sqsum_x register of the ce, scales it with vmax, imax, and the lsb, as given in the ce inter face description (see 5.4 ce interface description on page 100 ), and then performs a square - root operation. similarly, momentary real power and reactive power available via the wsum_x and varsum_x registers only have to be scaled by the host, while the apparent power has to be post - processed as follows: 2 2 q p s + = figure 22 illustrates the ce - to - host data flow. mpu ce i/o ram (configuration ram) pulses samples wpulse vpulse xpulseypulse control mux control control xram ce_busy xfer_busy tmux host spi data ready sag warning interrupt 71m6545/h dio1/interruptdio2/interrupt 10/7/2010 figure 22 : data flow in addition to the four pulse interrupts xpulse, ypulse, vpul se, and wpulse, the ce outputs two interrupt signals: ce_busy and xfer_busy. xfer_busy signals the end of an accumulation interval downloaded from: http:///
71m6545/71M6545H data sheet 70 v2 where data are ready for the host. this will occur whenever the ce has fi nished generating a sum by completing an accumulation interval as determined by the number of samples given in sum_samps . xfer_busy can be provided to the host via the test multiplexer output (tmux out) to support synchronization. the ypulse output can be used to signal a sag event to the host. refer to 5.4 ce interface description on page 100 for additional information on setting up the device by the host. for several reasons, it is necessary to have a small mpu program in f lash memory, even when the host takes over all post - processing: ? the mpu has to be prevented from executing code. with the flash mostly empty, the mpu will execute 0xff op - codes until it runs into the ce code image. executing the ce code image could have undesired results, e.g., changes to core i/o ram settings, and must the refore be avoided. ? the host cannot access the sfrs of the mpu directly. however, sf r access is required for accessing the dio pins. a small driver must exist to support sf r access, if the host needs to control the dio pins. sample mpu code that performs the tasks described above is available from maxim . during operation, the host needs to trigger the watchdog reset periodically in or der to avoid watchdog resets. downloaded from: http:///
71m6545/71M6545H data sheet v2 71 4 a pplication i nformation 4.1 connecting 5 v devices all digital input pins of the 71m6545/h are compatible with external 5 v devices. i/o pins configured as inputs do not require current - limiting resistors when they are connected to external 5 v devices. 4.2 directly connected sensor s figure 23 through figure 26 show voltage - sensing resistive dividers, current - sensing current transformers (cts) and current - sensing res is tive shunts and how they are connected to the voltage and current inputs of the 71m6545/h . all input signals to the 71m6545/h sensor inputs are voltage signals providing a scaled representation of either a sensed voltage or current. the analog input pins of the 71m6545/h are designed for sensors with low source impedance. rc filters with resistance values higher than those implemented in the demo boards must not be used . please refer to the demo board schematics for complete sensor input circui ts and corresponding component values. v in r out v3p3a vadcn (n = 8, 9 or 10) figure 23 : resistive voltage divide r (voltage sensing) i in iadcn v3p3a v out i out r burden ct 1:n noise filter (n = 0,1,...7) figure 24 . ct with single -ended input connection (current sensing) i in iadcn iadcn+1 v3p3a v out i out r burden ct 1:n bias network and noise filter (n = 0, 2, 4 or 6) figure 25 : ct with differential in put connection (current sensing) i in r shunt iadcn iadcn+1 v3p3a v out bias network and noise filter (n = 2, 4 or 6) figure 26 : differential resistive shunt connections (current sensing) downloaded from: http:///
71m6545/71M6545H data sheet 72 v2 4.3 system s using 71m6xx 3 isolated sensors and current shunts figure 27 shows a typical connection for current shunt sensors; using the 71m 6xx3 (poly - phase) isolated s ensor s . note that one shunt current sensor is connected without isolation, which is the neutral current sensor in this example ( connected to pins ia dc0 - ia dc1 ) . each 71m 6xx3 device is electrically isolated by a low - cost pulse transformer. th e 71m6545/h current sensor inputs must be configur ed for remote sensor communication s , as described in 2.2.8 . flexible remapping using the i/o ram registers muxn_sel[3:0] allows the sequence of analog input pins to be different from the standard configuration (a corresponding ce code must be used) . see figure 2 for the afe configuration corresponding to figure 27 . mpu rtc timers xin xout rx v3p3a v3p3 sys vbat_rtc gnda gndd dio ice load dio serial port oscillator/ pll mux and adc dio, pulses, leds compute engine flash memory ram 32 khz regulator power supply 71m6545/h temperature sensor vref pwr mode control pb neutral i 2 c or wire eeprom 10/7/2010 rtc battery v3p3d battery monitor spi interface host wpulse rpulse spi_ckispi_csz spi_dispi_do xfer_busy xpulseypulse sag tx 3.3 vdc pulses 24 t m u x iadc0 vadc8 ( va ) iadc 2 vadc9 (vb) iadc 4 vadc10 (vc) c ba neutral shunt resistor sensors iadc 6 iadc1 iadc 3 iadc 5 iadc 7 resistor dividers pulse transformers a b c } in* } ia } ib } ic 71m6xx371m6xx3 71m6xx3 this system is referenced to neutral *in = optional neutral current figure 27 : system using three- remotes and one - local (neutral) sensor downloaded from: http:///
71m6545/71M6545H data sheet v2 73 4.4 system using current transformers figure 28 shows a poly - phase system using four current transformers to support optional neutral c urrent sensing for anti - tamper purposes. the neutral current sensing ct can be omitted if neutral curren t sens ing is not required. the system is referenced to neutral (i.e., the neutr al rail is tied to v3p3a and v3p3sys). mpu rtc timers iadc0 vadc 8 ( va ) iadc 2 vadc9 (vb) xin xout rx v3p3a v3p3 sys vbat_rtc iadc 4 vadc10 (vc) gnda gndd dio ice phase a phase bphase c neutral load dio serial port oscillator/ pll mux and adc dio, pulses, leds compute engine flash memory ram 32 khz regulator current transformers power supply 71m6545/h temperature sensor vref iadc 6 pwr mode control pb neutral i 2 c or wire eeprom 10/7/2010 iadc1 iadc 3 iadc 5 iadc 7 rtc battery v3p3d battery monitor spi interface host resistor dividers wpulse rpulse spi_ckispi_csz spi_dispi_do xfer_busy xpulseypulse sag tx 3.3 vdc pulses 24 t m u x } *in } ia } ib } ic *in = optional neutral current this system is referenced to neutral figure 28 . system using current transformers downloaded from: http:///
71m6545/71M6545H data sheet 74 v2 4.5 metrology temperature compensation 4.5.1 distinction b etween standard and high - precision parts since the vref band - gap amplifier is chopper - stabilized, as set by the chop_e[1:0] (i/o ram 0x2106[3:2]) control field , the dc offset voltage, which is the most significant long - term drift mechanism in the voltage reference s (vref), is automatically removed by the chopper circuit. both the 71m6545/h and the 71m6xx3 feature chopper circuits for their respective vref voltage referenc e. since the variation in the bandgap reference voltage (vref) is the major contrib utor to me asurement error across temperatures , maxim implements a two step procedure to trim and characterize the vref voltage reference during the device manufacturing process . the first step in the process is applied to both the 71m6545 and 71M6545H parts. in this first step, the reference voltage (vref) is trimmed to a target value of 1.195v. during this trimming process, the trimt[7:0] ( i/o ram 0x2309 ) value is stored in non - vol atile fuses. trimt[7:0] is trimmed to a value that results in minimum vref variation with temperature. for the 71m6545 device , the trimt[7:0] value can be read by the mpu during initialization in order to calculate parabolic temperature compensation coefficients suitab le for each individua l 71m6545 device. the resulting temperature coefficient for vref in the 71m6545 is 40 ppm/ c. considering the factory calibration temperature of vref to be +22c and the industrial temperature range ( - 40 c to +85c), the vref error at the temperature extremes for the 71m6545 device can be calculated as: % 252 .0 2520 / 40 ) 22 85( += += ? ? ppm c ppm c c o o o and % 248 .0 2480 / 40 ) 22 40 ( ?= ?= ? ? ? ppm c ppm c c o o o the above calculation implies that both the voltage and the current measu rements are individually subject to a theoretical maximum error of approximatel y 0.25%. when the voltage sample and current sample are multiplied together to obtain the energy per sample, the vol tage error and current error combine resulting in approximately 0.5% maximum energy measurement error. however, this theoretical 0.5% error considers only the voltage reference (vref) as an error source. in practice, other error sources exist in the system. t he principal remaining error sources are the current sensors (shunts or cts) and their corresponding signal conditioning circuits, and the resistor voltage divider used to measure the voltage. the 71m6545 device should be used in class 1% de signs, to allow margin for the other error sources in the system. the 71M6545H goes through an additional process of characterization during production which makes it suitable to high - accuracy applications. the additional process is the characterization of the vol tage reference (vref) over temperature. the coefficients for the volt age reference are stored in additional non - volatile trim fuses. the mpu can read these trim fuses during initialization and calculate parabolic temperature compensation coefficients suitable for each individual 71M6545H device. the resulting temperature co efficient for vref in the 71M6545H is 1 0 ppm/ c. t he vref error at the temperature extremes for the 71M6545H device can be calculated as: % 063 .0 630 / 10 ) 22 85( += += ? ? ppm c ppm c c o o o and % 062 .0 620 / 10 ) 22 40 ( ?= ?= ? ? ? ppm c ppm c c o o o when the voltage sample and current sample are multiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately 0. 126 % maximum energy measurement error. the 71M6545H 0. 1 % grade device should be us ed in class 0.2 % and class 0.5% de signs, to allow margin for the other error sources in the syst em. the preceding discussion in this section also applies to the 71m6603 (0.5%), 71m6 11 3 (0.5%) and 71m6203 (0.1%) remote sensors. downloaded from: http:///
71m6545/71M6545H data sheet v2 75 4.5.2 temperature coefficients for the 71m6545 the equations provided below for calculating tc1 and tc2 apply to the 71m6545 . in order to obtain tc1 and tc2, the mpu reads trimt[7:0] ( i/o ram 0x2309 ) and uses the tc1 and tc2 equations provided . ppmc and ppmc2 are then calculated from tc1 and tc2, as shown. the resulting tracking of the refer ence voltage (vref) is within 4 0 ppm /c . see 4.5.1 distinction between standard and high - precision parts . trimt c v tc ? ? = 95.4 275 ) / (1 trimt c v tc ? ? ?= 00028 .0 557 .0 ) / (2 2 1 4632 .22 tc ppmc ? = 2 116 . 1150 2 tc ppmc ? = see 4.5.5 and 4.5.6 below for further temperature compensation details. 4.5.3 temperature coefficients for the 71M6545H for the 71M6545H , undergoes a two - pass factory trimming process which stores additional trim fuse value s. the additional trim fuse values characteriz e the devices vref behavior at various tempera tures. the values for tc1 and tc2 are calculated from the values read from the trimt[7:0] ( i/o ram 0x2309 ), trimbgb[15:0] (info page 0x92 and 0x93) and trimb gd[7:0] (info page 0x94) non - volatile on - chip fuses using the equations provided . the resulting tracking of the refer ence voltage is within 10 ppm /c, corresponding to a 0.126% energy measurement accuracy. the equations for deriving ppcm and ppmc2 f rom tc1 and tc2 are also provided . see 4.5.1 distinction between standard and high - precision parts . tc 1( v/ ) = 35 . 091 +0. 01764 ? trimt +1. 587 ? ( ??????? ? ??????? ) trimt c v tc ? ? ?= 00028 .0 557 .0 ) / (2 2 1 4632 .22 tc ppmc ? = 2 116 . 1150 2 tc ppmc ? = trimt[7:0] trims the vref voltage for minimum variation with temperature. the trimt[7:0] fuses are read by the mpu directly at i/o ram address 0x2309[7:0] . during the second pass trim for the 71M6545H , vref is further characterized at 85 c and 22 c, and t he resulting fuse trim values are stored in trimbgb[15:0] and trimbgd[7:0] , respectively. trimbgb[15:0] and trimbgd[7:0] cann ot be read directly by the mpu. see 5.3 reading the info page (71M6545H only) on page 98 for information on how to read the info page trim fuses. see 4.5.5 and 4.5.6 below for further temperature compensation details. 4.5.4 temperature coefficients for the 71m6 60 3 and 71m6103 ( 1% energy accuracy ) refer to the 71m6xxx data sheet for the equations that are applicable to each 71m6x x3 part number and the corresponding temperature coefficients. 4.5.5 temperature compensation for vref an d shunt sensors this section discusses metrology temperature compensation for the meter des igns where current shunt sensors are used in conjunction with the 71m6xx3 remote isolated sensors, as shown in fi gure 27 . s ensors that are directly connected to the 71m6545/h are affected by the voltage variation in the 71m6545/h vref due to temperature. on the other hand, shunt sensors that are connected to 7 1m 6xx3 remote sensor are affected by the vref in the 71m 6xx3 . the vref in both the 71m6545/h and 71m 6xx3 can be compensated digitally using a second - order polynomial function of temperature. the 71m6545/h and 71m 6xx3 feature temperature sensors for the purposes of temperature compensating their corresponding vref. the compensation computations must be implemented in mpu firmware . referring to figure 27 , the vadc8 ( va ) , vadc9 ( vb ) and vadc10 ( vc ) voltage sensors are always directly connected to the 71m6545/h . thus, the precision of the voltage sensors is primarily affected by vref in the 71m6545/h . the temperature coefficient of the resistors used to implement the voltage divider s downloaded from: http:///
71m6545/71M6545H data sheet 76 v2 for the voltage sensors (see figure 23 ) determine the behavior of the voltage division ratio with respect to temperature. it is recommended to use resistors with low temperature coefficients, while forming the entire voltage divider using resistors belonging to the same technology family , in o rder to minimize the temperature dependency of the voltage division ratio . the resistors must also have suitable voltage ratings. the 71m6545/h also may have one local current shunt sensor that is connected directly to it via the iadc0 - iadc1 input pins , a nd therefore this local current sensor is also affected by the vref in the 71m6545/h . the shunt current sensor resistance has a temperature dependency, which also may require compensation , depending on the required accuracy class . the i adc2 - iadc3 , i adc4 -i adc5 and i adc6 - iadc7 current sensors are isolated by the 71m 6xx3 and depend on the vref of the 71m 6xx3 , plus the variation of the corresponding remote shunt current sensor with temperature. the mpu has the responsibility of computing the necessary sample gain compensation values required for each sensor channel based on the sensed temperature. maxim provides demonstration code that implements the gain_adj x compensation equation shown below. the resulting gain_adj x values are stored by the mpu in five ce ram locations gain_adj0- gain_adj 5 ( ce ram 0x40 - 0x4 4 ). the demonstration code thus provides a suitable implementation of temperature compensation, but other methods are possible in mpu firmware by utilizing the on - chip temperature sensors while storing the sample gain adjustment results in the ce ram gain_adj x storage locations for use by the ce . the demonstration code maintains five separate sets of ppmc and ppmc 2 coefficients and computes five separate gain_adjx values based on the sensed temperature using the equation below: 23 2 14 2 2 _ 100 2 _ 10 16385 _ ppmc x temp ppmc x temp adjx gain ? ? + ? ? + = the gain_adj x values stored by the mpu in ce ram are used by the ce to gain adjust (i.e., multiply) the sample in each corresponding sensor channel. a gain_adj x value of 16,384 (i.e . , 2 14 )corresponds to unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify the samples. in the above equation , temp_x is the deviation from nominal or calibration temperature expressed in mul tiples of 0.1 c . th e 10x and 100x factors seen in the above equation are due to 0.1 o c scaling of temp_x . for example, if the calibration (reference) temperature is 22 o c and the measured temperature is 27 o c, then 10* temp_x = (27 - 22) x 10 = 50 (decimal), which represents a +5 o c deviation from 22 o c. in the demonstration code, temp_x is calculated in the mpu from the stemp[10:0] temperature sensor reading using the equation provided below and is scaled in 0.1c units. see 2.5.5 71m6545/h temperature sensor on page 53 for the equation to calculate temperature in degrees c from the stemp[10:0] value. table 57 shows the five gain_adj x equation output storage location s and the voltage or current sensor channels for which they compensate for the 1 local / 3 remote configuration shown in figure 27 . table 57 : gain_adjn compensation channels ( figure 2 , figure 27 , table 1 ) gain adjustment output ce ram address sensor channel(s) (pin names) compensation for: gain_adj0 0x40 vadc8 ( va ) vadc9 ( vb ) vadc10 ( vc ) vref in 71m6545/h and voltage divider resistors gain_adj 1 0x41 iadc0-iadc1 vref in 71m6545/h and shunt (neutral current) gain_adj 2 0x42 iadc2-iadc3 vref in 71m6xx3 and shunt (phase a) gain_adj 3 0x43 iadc4-iadc5 vref in 71m6xx3 and shunt (phase b) gain_adj 4 0x44 iadc6-iadc7 vref in 71m6xx3 and shunt (phase c) in the demonstration code, the shape of the temperature compensation second - order parabolic curve is determined by the values stored in the ppmc (1 st order coefficient) a nd ppmc2 (2 nd order coefficient) , which are typically setup by the mpu at initialization time from values that are stored in eep rom. downloaded from: http:///
71m6545/71M6545H data sheet v2 77 to disable temperature compensation in the demonstration code, ppmc and ppmc2 are both set to zero for each of the five gain_adj x channels. to enable temperature compensation, the ppmc and ppmc2 coefficients are set with values that match the expected temperature variation of the shunt current sensor (if required ) and the corresponding vref voltage reference (summed together) . the shunt sensor requires a second order polynomial compensation which is determined by the ppmc and ppmc2 coefficient s for the corresponding current measurement channel. the corresponding vref voltage reference also requires the ppmc and ppmc2 coefficients to match the second order temperature behavior of the voltage reference. the ppmc and ppmc2 values associated with the shunt and with the corresponding vref are summed together to obtain the compensation coefficients for a given current - sensing chan nel (i.e., the 1 st order ppmc coefficients are summed together, and the 2 nd order ppmc2 coefficients are summed together). in the 71m6545 , the required vref compensation coefficients ppmc and ppmc2 are calculated from readable on - chip non - volatile fuses (see 4.5.2 temperature coefficients for the 71m6545 ). these coefficients are designed to achieve 40 ppm/c for vref in the 71m6545 . ppmc and ppmc2 coefficients are similarly calculated for the 71m6xx3 remote sensor (see 4.5.4 ). for the 71M6545H , coefficients specific to each individual device can be calculated from values read from additional on - chip fuses that characterize the vref behavior of each individual part across industri al temperatures (see 4.5.3 temperature coefficients for the 71M6545H ) . the resulting tracking of the refer ence vref voltage is within 10 ppm /c . for the current channels, t o determine the ppmc and ppmc2 coefficient s for the shunt current sensors , the designer must either know the average temperature curve of the shunt from its manufacturers data sheet or obtain the se coefficients by laboratory characterization of the shunt used in the design. 4.5.6 temperature compensation of vref and current transformers this section discusses metrology temperature compensation for meter design s where current transformer (ct) sensors are used, as shown in figure 28 . sensors that are directly connected to the 71m6545/h are affected by the voltage variation in the 71m6545/h vref due to temperature. the vref in the 71m6545/h can be compensated digitally using a second - order polynomial function of temperature. the 71m6545/h features a temperature sensor for the purposes of temperature compensating its vref. the compensation computations must be implemented in mpu firmware and written to the corresponding gain_adjx ce ram location . referring to figure 28 , the vadc8 ( va ) , vadc9 ( vb ) and vadc10 ( vc ) voltage sensors are directly connected to the 71m6545/h . thus, the precision of the voltage sensors is primarily affected by vref in the 71m6545/h . the temperature coefficient of the resistors used to implement the v oltage dividers for the voltage senso rs (see figure 23 ) determine the behavior of the voltage division ratio with resp ect to temperature. it is recommended to use resistors with low temperature coefficients, while forming the entire voltage divider using resistors belonging to the same technology family , in order to minimize the temperature dependency of the voltage division ratio. the resistors must also have s uitable voltage rat ings. the current transformers are directly connected to the 71m6545/h and are therefore primarily affected by the vref temperature dependency in the 71m6545/h . for best performance, it is recommended to use the differential signal conditioning circuit, as shown in figure 25 , to connect the cts to the 71m6545/h . c urrent transformers may also require temperature compensation. the copper wire wi nding in the ct has dc resistance with a temperature coefficient, which makes the voltage delivered to the burden resistor temperature dependent, and the burden resistor also has a temperature coeffi cient. thus, each ct sensor channel needs to compensate for the 71m6545/h vref, and optionally for the temperature dependency of the ct and its burden resistor depending on the required accuracy class. the mpu has the responsibility of computing the necessary sample gain compensation values required for each sensor channel based on the sensed temperature. maxim provides de monstration code that implements the gain_adj x compensation equation shown below. the resulting gain_adj x values are stored by the mpu in five ce ram locations gain_adj0- gain_adj5 ( ce ram 0x40 - 0x4 4 ). the demonstration code thus provides a suitable implementation of temperature compensation, but other methods are possible in mpu firmware by utilizing the on - chip temperature sensor while storing the sample gain adjustment results in the ce ram gain_adjn storage locations. the demonstration code maint ains downloaded from: http:///
71m6545/71M6545H data sheet 78 v2 five separate sets of ppmc and ppmc 2 coefficients and computes five separate gain_adjn values based on the sensed temperature using the equation below: 23 2 14 2 2 _ 100 2 _ 10 16385 _ ppmc x temp ppmc x temp adjx gain ? ? + ? ? + = the gain_adjn values stored by the mpu in ce ram are used by the ce to gain adjust (i.e., multiply) the sample in each corresponding sensor channel. a gain_adj x value of 16,384 ( i.e. , 2 14 )corresponds to unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify the samples . in the above equation, temp_x is the deviation from nominal or calibration temperature expressed in mul tiples of 0.1 c . t he 10x and 100x factors seen in the above equation are due to 0.1 o c scaling of temp_x . for example, if the calibration (reference) temperature is 22 c and the measured temperature is 27 c, then 10* temp_x = (27 - 22) x 10 = 50 (decimal), which represents a +5 c deviation from 22 c. in the demonstration code, temp_x is calculated in the mpu from the stemp[10:0] temperature sensor reading using the equation provided below and is scaled in 0.1c units. see 2.5.5 71m6545/h temperature sensor on page 53 for the equation to calculate temperature in c from the stemp[10:0] reading. table 58 shows the five gain_adj x equation output storage locations and the voltage or current measurements for which they compensate. table 58 : gain_adj x compensation channels ( figure 3 , figure 28 , table 2 ) gain adjustment output ce ram address sensor channel(s) (pin names) compensation for: gain_adj0 0x40 vadc8 (va) vadc9 (vb ) vadc10 ( vc ) vref in 71m6545/h and voltage divider resistors gain_adj 1 0x41 iadc0-iadc1 vref in 71m6545/h, ct and burden resistor (neutral current) gain_adj 2 0x42 iadc2-iadc3 vref in 71m6545/h, ct and burden resistor ( phase a ) gain_adj 3 0x43 iadc4-iadc5 vref in 71m6545/h, ct and burden resistor ( phase b ) gain_adj 4 0x44 iadc6-iadc7 vref in 71m6545/h, ct and burden resistor ( phase c ) in the demonstration code, the shape of the temperature compensation second - order parabolic curve is determined by the values stored in the ppmc (1 st order coefficient) and ppmc2 (2 nd order coefficient), which are typically setup by the mpu at initialization time from values that are stored in eeprom. to disable temperature compensation in the demonstration code, ppmc and ppmc2 are both set to zero for each of the five gain_adj x channe ls. to enable temperature compensation, the ppmc and ppmc2 coefficients are set with values that match the expected vref temperature variation and optionally the corresponding sensor circuit (i.e., the ct and burden resistor for c urrent channels or the resistor divider network for the voltage channels) . in the 71m6545 , the required vref compensation coefficients ppmc and ppmc2 are calculated from readable on - chip non - volatile fuses (see 4.5.2 temperature coefficients for the 71m6545 ). these coefficients are designed to achieve 40 ppm / c for vref. for the 71M6545H , coefficients specific to each individual device can be calculated from value s read from additional on - chip fuses that characterize the vref behavior of each individual part acro ss industrial temperatures (see 4 .5.3 temperature coefficients for the 71M6545H ) . the resulting tracking of the refer ence vref voltage is within 10 ppm /c . downloaded from: http:///
71m6545/71M6545H data sheet v2 79 4.6 connecting i 2 c eeproms i 2 c eeproms or other i 2 c compatible devices should be connected to the dio pins dio 2 and dio 3 , as shown in figure 29 . pull - up resistors of roughly 10 k ? to v3p3d should be used for both sdck and sdata signals . the dio_eex ( i/o ram 0x2456[7:6] ) field must be set to 01 in order to convert the dio pins dio 2 and dio 3 to i 2 c pins scl and sdata . figure 29 : i 2 c eeprom connection 4.7 connecting three - wire eeproms wire eeproms and other compatible devices should be connected to the di o pins dio 2 and dio 3 , as described i n 2.5.11 eeprom interface on page 57 . 4.8 uart (tx/rx) the uart0 rx pin should be pulled down by a 10 k ? resistor and additionally protected by a 100 pf ce ramic capacitor, as shown in figure 30 . figure 30 : connections for the uart 4.9 connecting the reset pin even though a functional meter does not necessarily need a reset switch, it is useful to have a reset push button for prototyping as shown in figure 31 , left side. the reset signal may be sourced from v3p3sys . for a production meter, the reset pin should be protected by the external components shown in figure 31 , right side. r1 should be in the range of 100 ? and mounted as closely as possible to the ic. s ince the 71m6545/h generates its own power - on reset, a reset button or circuitry, as shown in figure 31 , is only required for test units and prototypes. tx rx 71m6545/h 10 k 100 pf rx tx dio 2 dio 3 eeprom sdck sda ta v3p3d 10 k 10 k 71m6545/h downloaded from: http:///
71m6545/71M6545H data sheet 80 v2 figure 31 : external components for the reset pin: push - button (left), production circuit (right) 4.10 connecting the emulator port pins even when the emulator is not used, small shunt capacitors to ground (22 pf) should be used for protection from emi as illustrated in figure 32 . production boards should have the ice_e pin connected to ground. figure 32 : external components for the emulator interface 4.11 flash programming 4.11.1 flash programming via the ice port operational or test code can be programmed into the flash memory using either an in - circuit emulator or the flash programmer module (tfp -2 ) available from maxim . the flash programming procedure uses the e_rst, e_rxtx, and e_tclk pins. 4.11.2 flash programming via the spi port it is possible to erase, read and program the flash memor y of the 71m6545/h via the spi port. see 2.5.12 for a detailed description. 4.12 mpu demonstration code all application - specific mpu functions mentio ned in 4 application information are featured in the demonstration c source code supplied by maxim . the code is available as part of the demo nstration kit for the 71m6545/h . the demonstrati on kits come with the 71m6545/h pre programmed with demo nstration firmware and mounted on a functional sample meter demo board . the demo boards allow for quick and efficient evaluation of the ic without having to write firmware or having to supply an in - circuit emulator (ice). e_rst 71m6545/h e_tclk 62 62 ? 62 ? 22 pf 22 pf 22 pf ice_e v3p3d e_rxt r 1 reset 71m6545/h gndd v3p3d r 2 v3p3d reset switch 1k 0.1f 10k 71m6545/h downloaded from: http:///
71m6545/71M6545H data sheet v2 81 4.13 crystal oscillator the oscillator of the 71m6545/h drives a standard 32.768 khz watch crystal. the oscillator has been designed specifically to handle these crystals and is compatible with thei r high impedance and limited power handling capability. the oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the vbat_rtc pin. board layouts with minimum capacitance from xin to xout require less battery current. good layouts have xin and xout shielded from each other and also keep the xin and xout trac es short and away from digital signals. since the oscillator is self - biasing, an external resistor must not be connected across the crystal. 4.14 meter calibration once the 71m6545/h energy meter device has been installed in a meter system, it must be calibrat ed . a complete calibration includes the following: ? establishment of the reference temperature for factory calibration (e.g., typically 22 c). ? calibration of the metrology section, i.e. , calibration for errors of the current sensors, voltage di viders and signal conditioning components as well as of the internal referenc e voltage (vref) at the reference temperature ( e.g. , typically 22 c). ? calibration of the oscillator frequency u sing the rtca _adj register ( i/o ram 0x2504 ). the metrology section can be calibrated using the gain and phase adjustment factors accessible to the ce . the gain adjustment is used to compensate for tolerances of components used for signal c onditioning, especially the resistive components . phase adjustment is provided to compensate for phase shifts introduc ed by the current sensors or by the effects of reactive power supplies . due to the flexibility of the mpu firmware, any calibration method, such as calibration based on energy, or current and voltage can be implemented . it is also possible to implement segment - wise calibration (de pending on current range). the 71m6545/h supports common industry standard calibration techniques, such as single - point (ene r gy - only), multi - point (energy, vrms, irms), and auto - calibration. maxim provides a calibration spreadsheet file to facilitate the calibration proces s. contact your maxim representative to obtain a copy of the latest calibration spreadsheet file for the 71m6545/h . downloaded from: http:///
71m6545/71M6545H data sheet 82 v2 5 firmware interface 5.1 i/o ram map C functional order in table 59 and table 60 , unimplemented (u) and reserved (r) bits are shaded in light gray. unimplemented bi ts are identified with a u. unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. reserved bits are identified with a n r, and must always be written with a zero. writing values other than zero to reserved bits may have undesirable side effects and must be avoided. non - volatile bits are shaded in dark gray. non - volatile bits are backed - up during power failures if the system includes a battery connected to the vbat _rtc pin and the pin voltage is within specification. the i/o ram locations listed in table 59 h ave sequential addresses to facilitate reading by the mpu (e.g., in order to v erify their contents). these i/o ram locations are u sually modified only at boot - up . the addresses shown in table 59 are an alternative sequential address to the addresses from table 60 which are used throughout this document. for instance, equ[2:0] can be accessed at i/o ram 0x200 0 [7:5] or at i/o ram 0x2106[7:5] . table 59 : i/o ram map C functional order, basic configuration name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ce6 2000 equ[2:0] u chop_e[1:0] rtm_e ce_e ce5 2001 u sum_samps[12:8] ce4 2002 sum_samps[7:0] ce3 2003 u u ce_lctn[5:0] ce2 2004 pls_maxwidth[7:0] ce1 2005 pls_interval[7:0] ce0 2006 diff6 _e diff4 _e diff2 _e diff0 _e rfly_dis fir_len [1:0] pls_inv rce0 2007 chopr[1:0] rmt6 _e rmt4 _e rmt2 _e tmuxr6 [2:0] rtmux 2008 u tmuxr4 [2:0] u tmuxr2 [2:0] fovrd 2009 u u r u u u u u mux5 200a mux_div[3:0] mux10_sel mux4 200b mux9_sel mux8_sel mux3 200c mux7_sel mux6_sel mux2 200d mux5_sel mux4_sel mux1 200e mux3_sel mux2_sel mux0 200f mux1_sel mux0_sel temp 2010 r temp_pwr osc_comp temp_bat u temp_per[2:0] dio_r5 201b u u u u u dio_rpb[2:0] dio_r4 201c u dio_r11[2:0] u dio_r10[2:0] dio_r3 201d u dio_r9[2:0] u dio_r8[2:0] downloaded from: http:///
71m6545/71M6545H data sheet v2 83 name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dio_r2 201e u dio_r7[2:0] u dio_r6[2:0] dio_r1 201f u dio_r5[2:0] u dio_r4[2:0] dio_r0 2020 u dio_r3[2:0] u dio_r2[2:0] dio0 2021 dio_eex[1:0] u u r r r r dio1 2022 dio_pw dio_pv r r u r r r dio2 2023 dio_px dio_py u u u u u u int1_e 2024 ex_eex ex_xpulse ex_ypulse ex_rtct u ex_rtc1m ex_rtc1s ex_xfer int2_e 2025 ex_spi ex_wpulse ex_vpulse reserved 2026 r r r r r sfmm 2080 sfmm[7:0]* sfms 2081 sfms[7:0]* notes: * sfmm and sfms are accessible only through the spi slave port. see 2.5.1.1 flash memory for d etails. downloaded from: http:///
71m6545/71M6545H data sheet 84 v2 table 60 lists bits and registers that may have to be accessed on a frequent basis. reserved bits have lighter gray background, and non - volatile bits have a darker gray background. table 60 : i/o ram map C functional order name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ce and adc mux5 2100 mux_div[3:0] mux10_sel[3:0] mux4 2101 mux9_sel[3:0] mux8_sel[3:0] mux3 2102 mux7_sel[3:0] mux6_sel[3:0] mux2 2103 mux5_sel[3:0] mux4_sel[3:0] mux1 2104 mux3_sel[3:0] mux2_sel[3:0] mux0 2105 mux1_sel[3:0] mux0_sel[3:0] ce6 2106 equ[2:0] u chop_e[1:0] rtm_e ce_e ce5 2107 u sum_samps[12:8] ce4 2108 sum_samps[7:0] ce3 2109 u u ce_lctn[5:0] ce2 210a pls_maxwidth[7:0] ce1 210b pls_interval[7:0] ce0 210c diff6 _e diff4 _e diff2 _e diff0 _e rfly_dis fir_len [1:0] pls_inv rtm0 210d u u u u u u rtm0[9:8] rtm0 210e rtm0[7:0] rtm1 210f rtm1[7:0] rtm2 2110 rtm2[7:0] rtm3 2111 rtm3[7:0] clock generation ckgn 2200 u u adc_div pll_fast reset mpu_div[2:0] vref trim fuses trimt 2309 trimt[7:0] dio dio 16 2420 u u dio 16[5:0] u u dio 32 243d u u dio 45[5:0] u u dio 38 2443 u u dio 51[5:0] u u dio 42 2447 u u dio 55[5:0] downloaded from: http:///
71m6545/71M6545H data sheet v2 85 name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dio_r5 2450 u r r r u dio_rpb[2:0] dio_r4 2451 u dio_r11[2:0] u dio_r10[2:0] dio_r3 2452 u dio_r9[2:0] u dio_r8[2:0] dio_r2 2453 u dio_r7[2:0] u dio_r6[2:0] dio_r1 2454 u dio_r5[2:0] u dio_r4[2:0] dio_r0 2455 u dio_r3[2:0] u dio_r2[2:0] dio0 2456 dio_eex[1:0] u u r r r r dio1 2457 dio_pw dio_pv r r u r r r dio2 2458 dio_px dio_py u u u u u u nv bits sparenv 2500 u u u u r fovrd 2501 u u r u u u u u tmux 2502 u u tmux[ 5 :0] tmux2 2503 u u u tmux2[4:0] rtc1 2504 u rtca_adj[6:0] 71m6xx3 interface remote2 2602 rmt_rd[15:8] remote1 2603 rmt_rd[7:0] rbits int1_e 2700 ex_eex ex_xpulse ex_ypulse ex_rtct u ex_rtc1m ex_rtc1s ex_xfer int2_e 2701 ex_spi ex_wpulse ex_vpulse u u u u u secure 2702 flsh_unlock[3:0] r flsh_rde flsh_wre r analog0 2704 vref_cal vref_dis pre_e adc_e bcurr spare[2:0] version 2706 version[7:0] intbits 2707 u int6 int5 int4 int3 int2 int1 int0 flag0 sfr e8 ie_eex ie_xpulse ie_ypulse ie_rtct u ie_rtc1m ie_rtc1s ie_xfer flag1 sfr f8 ie_spi ie_wpulse ie_vpulse u u u u pb_state stat sfr f9 u u u pll_ok u vstat[2:0] remote0 sfr fc u perr_rd perr_wr rcmd[4:0] spi1 sfr fd spi_cmd[7:0] spi0 2708 spi_stat[7:0] rce0 2709 chopr[1:0] rmt6 _e rmt4 _e rmt2 _e tmuxr6 [2:0] rtmux 270a u tmuxr4 [2:0] u tmuxr2 [2:0] downloaded from: http:///
71m6545/71M6545H data sheet 86 v2 name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 info_pg 270b u u u u u u u info_pg dio3 270c u u port_e spi_e spi_safe u u u nv ram and rtc nvramxx 2800 - 287f nvram[0] C nvram[7f] C direct access wake 2880 wake_tmr[7:0] stemp1 2881 stemp[10:3] stemp0 2882 stemp[2:0] u u u u u bsense 2885 bsense[7:0] lkpaddr 2887 lkpautoi lkpaddr[6:0] lkpdata 2888 lkpdat[7:0] lkpctrl 2889 u u u u u u lkp_rd lkp_wr rtc0 2890 rtc_wr rtc_rd u rtc_fail u u u u rtc2 2892 rtc_sbsc[7:0] rtc3 2893 u u rtc_sec[5:0] rtc4 2894 u u rtc_min[5:0] rtc5 2895 u u u rtc_hr[4:0] rtc6 2896 u u u u u rtc_day[2:0] rtc7 2897 u u u rtc_date[4:0] rtc8 2898 u u u u rtc_mo[3:0] rtc9 2899 rtc_yr[7:0] rtc10 289b u u u u u rtc_p[16:14] rtc11 289c rtc_p[13:6] rtc12 289d rtc_p[5:0] rtc_q[1:0] rtc13 289e u u rtc_tmin[5:0] rtc14 289f u u u rtc_thr[4:0] temp 28 a0 r temp_pwr osc_comp temp_bat tbyte_busy temp_per[2:0] reserved 28b0 r r r r r r u u reserved 28b1 u u r r r r r r misc 28b2 sleep r r u u u u u reserved 28b3 u u u r r r r r wdrst 28b4 wd_rst temp_start u u u u u u mpu ports downloaded from: http:///
71m6545/71M6545H data sheet v2 87 name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port3 sfr b0 dio_dir[15:12] dio[15:12] port2 sfr a0 dio_dir[11:8] dio[11:8] port1 sfr 90 dio_dir[7:4] dio[7:4] port0 sfr 80 dio_dir[3:0] dio[3:0] flash erase sfr 94 flsh_erase[7:0] flshctl sfr b2 preboot secure u u flsh_pend flsh_pstwr flsh_meen flsh_pwe pgadr sfr b7 flsh_pgadr[6:0] u i 2 c eedata sfr 9e eedata[7:0] eectrl sfr 9f eectrl[7:0] downloaded from: http:///
71m6545/71M6545H data sheet 88 v2 5.2 i/o ram map C alphabetical order table 61 lists i/o ram bits and registers in alphabetical order. bits with a write direction (w in column dir ) are written by the mpu into configuration ram. typically, they are init ially stored in f lash memory and copied to the configuration ram by the mpu. some of the more frequently program med bits are mapped to the mpu sfr memory space. the remaining bits are mapped to the address space 0x2xxx. bits with r (read) direction can be read by the mpu. columns labeled rst and w k describe the bit values upon reset and wake, respectively. no entry in one of these col umns means the bit is either read - only or is powered by the nv supply and is not initia lized. write - only bits return zero when they are read. locations that are shaded in grey are non - volatile (i.e., battery - backed) . table 61 : i/o ram map C alphabetical order name location rst wk dir description adc_e 2704[4] 0 0 r/w enables adc and vref. when disabled, reduces bias current . adc_div 2200[5] 0 0 r/w adc_div c ontrols the rate of the adc and fir clocks. the adc_div setting determines whether mck is divided by 4 or 8: 0 = mck/4 1 = mck/8 the resulting adc and fir clock is as shown below. pll_fast = 0 pll_fast = 1 mck 6.291456 mhz 19.660800 mhz adc_div = 0 1.572864 mhz 4.9152 mhz adc_div = 1 0.786432 mhz 2.4576 mhz bcurr 2704[3] 0 0 r/w connects a 100 a load to the batter y (vbat_rtc pin) . bsense[7:0] 2885[7:0] C C r the result of the vbat_rtc pin measurement. see 2.5.7 71m6545/h battery monitor on page 55 . ce_e 2106[0] 0 0 r/w ce enable. ce_lctn[5:0] 2109[5:0] 31 31 r/w ce program location. the starting address for the ce program is 1024* ce_lctn . chip_id[15:8] chip_id[7:0] 2300[7:0] 2301[7:0] 0 0 0 0 r r these bytes contain the chip identification . chop_e[1:0] 2106[3:2] 0 0 r/w chop enable for the reference bandgap circuit. the value of chop change s on the rising edge of the internal muxsync signal according to the value in chop_e[1:0] : 00 = toggle 1 01 = positive 10 = reversed 11 = toggle 1 except at the mux sync edge at the end of an accumulation interval . downloaded from: http:///
71m6545/71M6545H data sheet v2 89 name location rst wk dir description chopr[1: 0] 2709[7:6] 00 00 r/w the chop settings for the remote sensor. 00 = auto chop. change every mux frame. 01 = positive 10 = negative 11 = auto chop (s ame as 00 ) diff0 _e 210c[4] 0 0 r/w enables iadc0 - iadc1 differential configuration. diff2 _e 210c[5] 0 0 r/w enables iadc2 - iadc3 differential configuration. diff4 _e 210c[6] 0 0 r/w enables iadc4 - iadc5 differential configuration. diff6 _e 210c[7] 0 0 r/w enables iadc6 - iadc7 differential configuration. dio_r2[2:0] dio_r3[2:0] dio_r4[2:0] dio_r5[2:0] dio_r6[2:0] dio_r7[2:0] dio_r8[2:0] dio_r9[2:0] dio_r10[2:0] dio_r11[2:0] dio_rpb[2:0] 2455[2:0] 2455[6:4] 2454[2:0] 2454[6:4] 2453[2:0] 2453[6:4] 2452[2:0] 2452[6:4] 2451[2:0] 2451[6:4] 2450[2:0] 0 0 0 0 0 0 0 0 0 0 0 C r/w connects pb and dedicated i/o pins dio2 through dio11 to internal resources. if more than one input is connected to the same resource, the multiple col umn below specifies how they are combined. dio_rx resource multiple 0 none C 1 reserved or 2 t0 (timer0 clock or gate) or 3 t1 (timer1 clock or gate) or 4 io interrupt (int0) or 5 io interrupt (int1) or dio_dir[1 4 :12] dio_dir[11:8] dio_dir[7:4] dio_dir[3:0] sfr b0[ 6 :4] sfr a0[7:4] sfr 90[7:4] sfr 80[7:4] f f r/w programs the direction of the first 1 5 dio pins. 1 indicates output. see dio_pv and dio_pw for special option for dio0 and dio1 outputs. see dio_eex [1:0] for special option for dio 2 and dio 3. note that the direction of dio pins above 1 4 is set by diox[1] . see port_e to avoid power up spikes. dio[1 4 :12] dio[11:8] dio[7:4] dio[3:0] sfr b0[3:0] sfr a0[3:0] sfr 90[3:0] sfr 80[3:0] f f r/w the value on the first 1 5 dio pins. when written, changes data on pins configured as outputs. pins as input ignore writes. note that the data for dio pins above 1 4 is set by diox[0] . dio_eex[1:0] 2456[7:6] 0 C r/w when set, converts dio 3 and dio 2 to interface with external eeprom. dio 2 becomes sdck and dio 3 becomes bi - directional sdata . dio_eex[1:0] function 00 disable eeprom interface 01 2- wire eeprom interface 10 3- wire eeprom interface 11 3- wire eeprom interface with separate do ( dio 3) and di ( dio 8) pins. downloaded from: http:///
71m6545/71M6545H data sheet 90 v2 name location rst wk dir description dio_pv 2457[6] 0 C r/w causes v pulse to be output on dio 1. dio_pw 2457[7] 0 C r/w causes wpulse to be output on dio 0. dio_px 2458[7] 0 C r/w causes xpulse to be output on dio 6. dio_py 2458[6] 0 C r/w causes ypulse to be output on dio 7. eedata[7:0] sfr 9e 0 0 r/w serial eeprom interface data . eectrl[7:0] sfr 9f 0 0 r/w serial eeprom interface control . status bit name read/ write reset state polarity description 7 error r 0 positive 1 when an illegal command is received. 6 busy r 0 positive 1 when serial data bus is busy. 5 rx_ack r 1 positive 1 indicates that the eeprom sent an ack bit. equ[2:0] 2106[7:5] 0 0 r/w specifies the power equation. equ[2:0] description element 0 element 1 element 2 recommended mux sequence 3 2 element, 4w, 3 d el ta va( ia - ib)/ 2 0 vc ic ia va ib ic vc 4 2 element, 4w, 3 wye v a(ia -ib)/2 vb(ic - ib)/2 0 ia va ib vb ic 5* 3 element, 4w, 3 w ye va ia vb ib vc ic ia va ib vb ic vc note: *the available ce codes implements only equation 5. contact your local maxim representative to obtain ce code for equations 3 and 4. ex_xfer ex_rtc1s ex_rtc1m ex_rtct ex_spi ex_eex ex_xpulse ex_ypulse ex_wpulse ex_vpulse 2700[0] 2700[1] 2700[2] 2700[3] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] 0 0 r/w interrupt enable bits. these bits enable the xfer_busy, the rtc_1sec, et c. the bits are set by hardware and cannot be set by writing a 1. the bits are reset by writing 0. note that if one of these interrupts is to enabled, its corresponding 8051 ex ena ble bit must also be set. see 2.4.10 interrupts , for details . downloaded from: http:///
71m6545/71M6545H data sheet v2 91 name location rst wk dir description fir_len [1:0] 210c[2:1] 0 0 r/w determines t he number of adc cycles in the adc decimation fir filter. pll_fast = 1: fir_len[1:0] adc cycles 00 141 01 288 10 384 pll_fast = 0: fir_len[1:0] adc cycles 00 135 01 276 10 not allowed the adc lsb size and full - scale values depend on the fir_len[1:0] setting. refer to table 73 on page 106 and table 91 on page 121 for details. flsh_erase[7:0] sfr 94[7:0] 0 0 w flash erase initiate flsh_erase is used to initiate either the flash mass erase cycle or the flash page erase cycle. specific patterns are expected for flsh_erase in order to initiate the appropriate erase cycle. (default = 0x00). 0x55 C initiate flash page erase cycle. must be proceeded by a write to flsh_pgadr [6:0] ( sfr 0xb7 ). 0xaa C initiate flash mass erase cycle. must be proceeded by a write to flsh_meen ( sfr 0xb2 ) and the debug (cc) port must be enabled. any other pattern written to flsh_erase ha s no effect. flsh_meen sfr b2[1] 0 0 w mass erase enable 0 = mass erase disabled (default). 1 = mass erase enabled. must be re - written for each new mass erase cycle . flsh_pend sfr b2[3] 0 0 r indicates that a posted flash write is pending. if another flash write is attempted, it is ignored. flsh_pgadr[6:0] sfr b7[7:1] 0 0 w flash page erase address flash page address (page 0 thru 63) that is erased during the page erase cycle. (default = 0x00). must be re - written for each new page erase cycle. flsh_pstwr sfr b2[2] 0 0 r/w enables posted flash writes. when 1, and if ce_e = 1, flash write requests are stored in a one element deep fifo and are executed when ce_busy falls. flsh_pend can be read to determine the status of the fifo. if flsh_pstwr = 0 or if ce_e = 0, flash writ es are immediate. downloaded from: http:///
71m6545/71M6545H data sheet 92 v2 name location rst wk dir description flsh_pwe sfr b2[0] 0 0 r/w program write enable 0 = movx commands refer to external ram space, normal operation (defau lt). 1 = movx @ dptr ,a moves a to external program space (flash) @ dptr . this bit is automatically reset after each byte written to flash. writes to this bit are inhibited when interrupts are enabled. flsh_rde 2702[2] C C r indicates that the flash may be read by ice or spi slave. flsh_rde = (! secure ) flsh_unlock[3:0] 2702[7:4] 0 0 r/w must be a 2 to enable any flash modification. see the description of flash se curity for more details. flsh_wre 2702[1] C C r indicates that the flash may be written through ice or spi slave ports. ie_xfer ie_rtc1s ie_rtc1m ie_rtct ie_spi ie_eex ie_xpulse ie_ypulse ie_wpulse ie_vpulse sfr e8[0] sfr e8[1] sfr e8[2] sfr e8[3] sfr f8[7] sfr e8[7] sfr e8[6] sfr e8[5] sfr f8[ 6] sfr f8[ 5] 0 0 r/w interrupt flags for external interrupts 2 and 6. these flags monitor the source of the int6 and int2 interrupts (external interrupts to the mpu core) . the se flags are set by hardware and must be cleared by the software interrupt handler. the iex2 ( sfr 0xc0[1] ) and iex6 ( sfr 0xc0[5] ) interrupt flags are automatically cleared by the mpu core when it vectors to the interrupt handler. iex2 and iex6 must be cleared by writing zero to their corresponding bit positions in sfr 0xc0, while writing ones to the other bit positions that are not being cleared. intbits 2707[6:0] C C r interrupt inputs. the mpu may read these bits to see the input to external in terrupts int0, int1, up to int6. these bits do not have any memory and are primari ly intended for debug use. lkpaddr[6:0] 2887[6:0] 0 0 r/w the address for reading and writing the rtc lookup ram . lkpautoi 2887[7] 0 0 r/w auto - increment flag. when set, lkpaddr [6:0] auto increment s every time lkp_rd or lkp_wr is pulsed. the incremented address can be read at lkpaddr. lkpdat[7:0] 2888[7:0] 0 0 r/w the data for reading and writing the rtc lookup ram. lkp_rd lkp_wr 2889[1] 2889[0] 0 0 0 0 r/w r/w strobe bits for the rtc lookup ram read and write. when set, the lkpaddr [6:0] and lkpdat registers is used in a read or write operation. when a strobe is set, it stay s set until the operation completes, at which time the strobe is cleared and lkpaddr [6:0] is incremented if lkpautoi is set. mpu_div[2:0] 2200[2:0] 0 0 r/w mpu clock rate is: mpu rate = mck rate * 2 - (2+ mpu_div [2:0]) . the maximum value for mpu_div[2:0] is 4. based on the default values of the pll_fast bit and mpu_div[ 2:0 ] , the power up mpu rate is 4.92mhz * ? = 1.23 mhz. the minimum mpu clock rate is 38.4 khz when pll_fast = 1. mux0_sel[3:0] 2105[3:0] 0 0 r/w selects which adc input is to be converted during time slot 0. mux1_sel[3:0] 2105[7:4] 0 0 r/w selects which adc input is to be converted during time slot 1. downloaded from: http:///
71m6545/71M6545H data sheet v2 93 name location rst wk dir description mux2_sel[3:0] 2104[3:0] 0 0 r/w selects which adc input is to be converted during time slot 2. mux3_sel[3:0] 2104[7:4] 0 0 r/w selects which adc input is to be converted during time slot 3. mux4_sel[3:0] 2103[3:0] 0 0 r/w selects which adc input is to be converted during time slot 4. mux5_sel[3:0] 2103[7:4] 0 0 r/w selects which adc input is to be converted during time slot 5. mux6_sel[3:0] 2102[3:0] 0 0 r/w selects which adc input is to be converted during time slot 6. mux7_sel[3:0] 2102[ 7:4 ] 0 0 r/w selects which adc input is to be converted during time slot 7. mux8_sel[3:0] 2101[3:0] 0 0 r/w selects which adc input is to be converted during time slot 8. mux9_sel[3:0] 2101[ 7:4 ] 0 0 r/w selects which adc input is to be converted during time slot 9. mux10_sel[3:0] 2100[3:0] 0 0 r/w selects which adc input is to be converted during time slot 10. mux_div[3:0] 2100[7:4] 0 0 r/w mux_div[3:0] is the number of adc time slots in each mux frame. the maximum number of time slots is 11. reserved 2457[0] 0 C r/w reserved. must be 0. reserved 2457[5:4] 00 C r/w reserved. must be 00. dio55 _en 2457[2] 0 C r/w enables dio55 dio55 _en = 0: dio55 is disabled dio55 _en = 1: dio55 is enabled reserved 2457[1] 0 C r/w reserved. must be 0. reserved 2456[3:0 ] 0000 C r/w reserved. must be 0000. osc_comp 28a0[5] 0 C r/w enables the automatic update of rtc_p [16:0] and rtc_q [1:0] every time the temperature is measured. pb_state sfr f8[0] 0 0 r the de - bounced state of the pb pin. perr_rd perr_wr sfr fc[6] sfr fc[5] 0 0 r/w the 71m6545/h sets these bits to indicate that a parity error on the remote sensor has been detected. once set, the bits are remembered until they are cleared by the mpu. pll_ok sfr f9[4] 0 0 r indicates that the clock generation pll is settled. pll_fast 2200[4] 0 0 r/w controls the speed of the pll and mck. 1 = 19.66 mhz (xtal * 600) 0 = 6.29 mhz (xtal * 192 ) pls_maxwidth[7:0] 210a[7:0] ff ff r/w determines the maximum width of the pulse (low - going pulse). maximum pulse width is (2* pls_maxwidth + 1)*t i . where t i is pls_interval . if pls_interval = 0 or pls_maxwidth =255, no width checking is performed and the output pulses have 50% duty cycle. downloaded from: http:///
71m6545/71M6545H data sheet 94 v2 name location rst wk dir description pls_interval[7:0] 210b[7:0] 0 0 r/w determines the interval time. the time between fifo outputs is pls_interval [7:0] *4*203ns. if pls_interval [7:0] = 0, the fifo is not used and pulses are output as soon as the ce issues them. assuming a that the ce code is written to generate 6 pulses in one integration interval, w hen the fifo is enabled (i.e., pls_interval [7:0] 0) and sum_samps = 2520, pls_interval [7:0] must be written with 81 so that the six pulses are evenly spaced in time over the integration interval and the last pulse is issued just prior to the end of the interval . pls_inv 210c[0] 0 0 r/w inverts the polarity of wpulse , varpulse , xpulse, and ypulse . normally, these pulses are active low. when inverted, they become active high. port_e 270c[5] 0 0 r/w enables outputs from the dio 0- dio1 4 pins. port_e = 0 blocks the momentary output pulse that occurs when dio0 - dio1 4 are reset on power up. pre_e 2704[5] 0 0 r/w enables the 8x pre - amp lifier . preboot sfrb2[7] C C r indicates that pre - boot sequence is active. rcmd[4:0] sfr fc[4:0] 0 0 r/w when the mpu writes a non - zero value to rcmd , the 71m6545/h issues a command to the appropriate remote sensor. when the command is complete, the 71m6545/h clears rcmd. reset 2200[3] 0 0 w when set, c ause s a reset. rfly_dis 210c[3] 0 0 r/w controls how the 71m6545/h drives the power pulse for the 71m6xxx. when set, the power pulse is driven high and low. when cleared, it is driven high followed by an open circuit flyback interval. rmt2 _e rmt4 _e rmt6 _e 2709[3] 2709[4] 2709[5] 0 0 r/w enables the remote interface. rmt_rd[15:8] rmt_rd[7:0] 2602[7:0] 2603[7:0] 0 0 r response from remote read request. rtca _adj[6:0] 2504 [6:0] 40 C r/w register for analog rtc frequency adjust ment . rtc_fail 2890[4] 0 0 r/w indicates that a count error has occurred in the rtc and that the time is not trustworthy. this bit can be cleared by writing a 0 . rtc_p[16:14] rtc_p[13:6] rtc_p[5:0] 289b[2:0] 289c[7:0] 289d[7:2] 4 0 0 4 0 0 r/w rtc adjust. see 2.5.4 real - time clock (rtc) . 0x0ffbf rtc_p 0x10040 note: rtc_p[16:0] and rtc_q[1:0] form a single 19 - bit rtc adjustment value. rtc_q[1:0] 289d[1:0] 0 0 r/w rtc adjust. see 2.5.4 real - time clock (rtc) . note: rtc_p[16:0] and rtc_q[1:0] form a single 19 - bit rtc adjustment value. rtc_rd 2890[6] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu reads. when rtc_rd is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. rtc_sbsc[7:0] 2892[7:0] C C r time remaining since the last 1 second boundary. lsb=1/128 second. downloaded from: http:///
71m6545/71M6545H data sheet v2 95 name location rst wk dir description rtc_tmin[5:0] 289e[5:0] 0 C r/w the target minutes register. see rtc_thr below . rtc_thr[4:0] 289f[4:0] 0 C r/w the target hours register. the rtc_t interrupt occur s when rtc_min [5:0] becomes equal to rtc_tmin[5:0] and rtc_hr[4:0] becomes equal to rtc_thr[4:0] . rtc_wr 2890[7] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu writes . when rtc_wr is cleared, the contents of the shadow register are written to the rtc counter on the next rtc clock (~1 khz). when rtc_wr is read, it return s 1 as long as rtc_wr is set. it c ontinue s to return one until the rtc counter actually updates. rtc_sec[5:0] rtc_min[5:0] rtc_hr[4:0] rtc_day[2:0] rtc_date[4:0] rtc_mo[3:0] rtc_yr[7:0] 2893[5:0] 2894[5:0] 2895[4:0] 2896[2:0] 2897[4:0] 2898[3:0] 2899[7:0] C C C C C C C C C C C C C C r/w the rtc interface. these are the year, month, day, hour, minute and second parameters for the rtc. the rtc is set by writing to these registers. year 00 and all others divisible by 4 are defined as a leap year. sec 00 to 59 min 00 to 59 hr 00 to 23 (00=midnight) day 01 to 07 (01=sunday) date 01 to 31 mo 01 to 12 yr 00 to 99 each write operation to one of these registers must be preceded by a write to 0x20a0. rtm_e 2106[1] 0 0 r/w real time monitor enable. when 0, the rtm output is low. rtm0[9:8] rtm0[7:0] rtm1[7:0] rtm2[7:0] rtm3[7:0] 210d[1:0] 210e[7:0] 210f[7:0] 2110[7:0] 2111[7:0] 0 0 0 0 0 0 0 0 0 0 r/w four rtm probes. before each ce code pass, the values of these registers ar e serially output on the rtm pin. the rtm registers are ignored when rtm_e = 0. note that rtm0 is 10 bits wide. the others assume the upper two bits are 00. secure sfr b2[6] 0 0 r/w inhibits erasure of page 0 and flash memory addresses above the beginning of ce code as defined by ce_lctn[5:0]. also inhibits the reading of flash memory by ex ternal devices (spi or ice port). sleep 28b2[7] 0 0 w puts the 71m6545/h to sleep. ignored if system power is present. the 71m6545/h wake s when the wake timer times out, when push button is pushed, or when system power returns. spi_cmd sfr fd[7:0] C C r spi command. 8- bit command from the bus master. spi_e 270c[4] 1 1 r/w spi port enable. enables the spi interface on pins spi_di, spi_do, spi_csz and spi_cki. spi_safe 270c[3] 0 0 r/w l imits spi writes to spi_cmd and a 16 byte region in dram. no other writes are per mitted. downloaded from: http:///
71m6545/71M6545H data sheet 96 v2 name location rst wk dir description spi_stat 2708[7:0] 0 0 r spi_stat contains the status results from the previous spi transaction bit 7 - 71m6545/h ready error: the 71m6545/h was not ready to read or write as directed by the previous command. bit 6 - read data parity: this bit is the parity of all bytes read from the 71m6545/h in the previous command. does not include the spi_stat byte. bit 5 - wr ite data par ity: this bit is the overall parity of the bytes written to the 71m6545/h in the previous command. i t includes cmd and addr bytes. bit 4:2 - bottom 3 bits of the byte count. does not in clude addr and cmd bytes. one, two, and three byte instructions return 111. bit 1 - spi flash mode: this bit is zero when the test pin is zero. bit 0 - spi flash mode ready: used in spi flash mode. indicates that the flash is ready to receive another write instruction. stemp[10:3] stemp[2:0] 2881[7:0] 2882[7:5] C C C C r r the result of the temperature measurement. sum_samps[12:8] sum_samps[7:0] 2107[4:0] 2108[7:0] 0 0 r/w the number of multiplexer cycles (frames) per xfer_busy interrupt. maximum value is 8191 cycles. tbyte_busy 28a0[3] 0 0 r indicates that hardware is still writing the 0x 28a0 byte. additional writes to this byte are locked out while it is one. write duration could be as long as 6 ms. temp_22[10:8] temp_22[7:0] 230a[2:0] 230b[7:0] 0 C r storage location for stemp [10:0] at 22c. stemp [10:0] is an 11 bit word. temp_bat 28a0[4] 0 C r/w causes vbat _rtc to be measured whenever a temperature measurement is per formed. reserved 28a0[7 ] 0 C r/w reserved. must always be zero. temp_per[2:0] 28a0[2:0] 0 C r/w sets the period between temperature measurements. automatic measurements can be enabled in any mode (msn or slp). temp_per = 0 disables automatic temperature updates, in which case temp_start may be used by the mpu to initiate a one - shot temperature measurement. temp_per time (seconds) 0 no temperature updates 1-6 ) per _ temp 3( 2 + 7 continuous updates temp_pwr 28a0[6 ] 0 C r/w selects the power source for the temp sensor: 1 = v3p3d, 0 = vbat_rtc. this bit is ignored in slp mode, where the temp sensor is always powered by vbat_rtc. downloaded from: http:///
71m6545/71M6545H data sheet v2 97 name location rst wk dir description temp_start 28b4[6] 0 0 r/w when temp_per = 0 automatic temperature measurements are disabled, and temp_start may be set by the mpu to initiate a one - shot temperature measurement. temp_start is i gnored in slp mode. hard ware clears temp_start when the temperature measurement is complete. tmux[ 5 :0] 2502[5 :0] C C r/w selects one of 32 signals for tmuxout. see 2.5.14 for details. tmux2[ 4 :0] 2503[4:0] C C r/w selects one of 32 signals for tmux2out. see 2.5.14 for details. tmuxr2 [2:0] tmuxr4 [2:0] tmuxr6 [2:0] 270a[2:0] 270a[6:4] 2709[2:0] 000 000 r/w the tmux setting for the remote isolated sensors (71m6xx 3 ). version[7:0] 2706[7:0] C C r the silicon version index. this word may be read by firmware to determine the silicon version. version[7:0] silicon version 0001 0001 a01 0001 001 1 a03 0001 001 1 b01 vref_cal 2704[7] 0 0 r/w brings the adc reference voltage out to the vref pin. this feature is disabl ed when vref_dis =1. vref_dis 2704[6] 0 1 r/w disables the internal adc voltage reference. vstat[2:0] sfr f9[2:0] C C r this word describes the source of power and the status of the vdd. vstat[2:0] description 000 system power ok. v3p3a>3.0v. analog modules are functional and accurate. [v3aok,v3ok]=11 001 system power low. 2.8v2.25v. full digital functionality. [v3aok,v3ok]=00 , [vddok,vddgt2]=11 011 vdd>2.0. flash writes are inhibited. if the trimvdd[5] fuse is blown, pll_fast is cleared. [v3aok,v3ok]=00 , [vddok,vddgt2]=01 101 vdd<2.0. when vstat=101, processor is nearly out of voltage. processor failure is imminent. [v3aok,v3ok]=00 , [vddok,vddgt2]=00 wake_tmr 2880[7:0] 0 C r/w timer duration is wake_tmr+1 seconds. wd_rst 28b4[7] 0 0 w reset the wd timer. the wd is reset when a 1 is written to this b it. writing a one clears and restarts the watch dog timer. downloaded from: http:///
71m6545/71M6545H data sheet 98 v2 5.3 reading the info page ( 71M6545H only) high precision trim fuse values provided in the 71M6545H device cannot be directly accessed through the i/o ram space. these trim fuses reside in a special area termed the info page. the mpu gains access to the info page by setting the info_pg ( i/o ram 0 x270b[0] ) control bit. once the info_pg bit is set, info page contents are accessible in program memory space based at the address specif ied by the contents of ce_lctn[5:0] ( i/o ram 0x2109[5: 0] ). ce_lctn[5:0] specifies a base address at a 1kb address bound ary. thus, the base address for the info page is at 1024* ce_lctn[5 :0] . table 62 provides a list of the available 71M6545H trim fuses and their corresponding offsets relative to the info page base address. after reading the desired info page information, the mpu must reset the info_pg bit. table 62 . info page trim fuses trim fuse object size address offset comments temp_85[10:8] temp_85[7:0] (11 - bits) 8- bits 8- bits 0x90 0x91 temp_85[10:0] holds the stemp[10:0] reading at 85c. 2s complement format trimbgb[15:8] trimbgb[7:0] (16 - bits) 8- bits 8- bits 0x92 0x93 t rimbgb[15:0] holds the deviation of vref from its ideal value (1.195v) at 85c. lsb = 0.1 mv 2s complement format trimbgd[7:0] (8 - bits) 8- bits 0x94 t rimbgd[7:0] holds the deviation of vref from its ideal value (1.195v) at 22c. lsb = 0.1 mv 2s complement format figure 33 . trim fuse bit mapping offset name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x90 temp_85[10:0] temp_85[10:8] 0x91 temp_85[7:0] 0x92 trimbgb[15:0] trimbgb[15:8] 0x93 trimbgb[7:0] 0x94 trimbgd[7:0] trimbgd[7:0] the code below provides an example for reading info page fuse trims . in this code example, the address, "px" is a pointer to the mpu s code space. in assembly language, the info page data objects, which are read - only , must be accessed with the movc 8051 instruction. in c, info page trim fuses must be fetched with a pointer of the correct wi dth, depending whether an 8 - bit or a 16 - bit data object is to be fetched. the case statements in the code example below perform casts to obtain a pointer of the correct size for each object, as needed. in assembly language, the mpu has to form 11 - bit or 16 - bit values from two separate 8 - bit fetches, depending on the object being fetched. the byte values containing less than 8 valid bits are lsb justified. for exampl e info page offset 0x90 is an 8 - bit object, whose three lsbs are bits [10:8] of the complete temp_85[10:0] 11 - bit object. the info page data objects are 2s complement format and should be sign extended when read into a 16 - bit data type (see case _temp85 in the code example). downloaded from: http:///
71m6545/71M6545H data sheet v2 99 #if high_precision_meter int16_t read_trim (enum etrimsel select) { uint8r_t *px; int16_t x; px = ((uint16_t)select) + ((uint8r_t *)(ce3 << 10)); switch (select) { default: case _trimbgd: info_pg = 1; x = *px; info_pg = 0; break; case _trimbgb: info_pg = 1; x = *(uint16r_t*)px; info_pg = 0; break; case _temp85: info_pg = 1; x = *(u int16r_t*)px; info_pg = 0; if (x & 0x800) x |= 0xf800; break; } return (x); } #endif //#if high_precision_meter downloaded from: http:///
71m6545/71M6545H data sheet 100 v2 5.4 ce interface description 5.4.1 ce program the ce performs the precision computations necessary to accurately measure po wer. these computa tions include offset cancellation, phase compensation, product smoothing, p roduct summation, frequency de tection, var calculation, sag detec tion and voltage phase measurement. all data computed by the ce is dependent on the selected meter equation as given by equ[2:0] ( i/o ram 0x2106[7:5] ). the standard ce program is supplied by maxim as a data image that can be merged with the mpu op erational code for meter applications . typically, this ce program covers most applications and does not need to be modified . other variations of ce code may be available from maxim . the description in this section applies to ce code revision ce43 a01a . 5.4.2 ce data format all ce words are 4 bytes . unless specified otherwise, they are in 32 - bit twos complement format (- 1 = 0xffffffff) . calibration para meters are defined in flash memory (or external eeprom) and must be copied to ce data memory by the mpu before enabling the ce . internal variables are used in internal ce calculations . input variables allow the mpu to control the behavior of the ce code . output variables are outputs of the ce calculations . the corresponding mpu address for the most signi ficant byte is given by 0x0000 + 4 x ce_add ress and by 0x0003 + 4 x ce_address for the least significant byte. 5.4.3 constants constants used in the ce data memory tables are: ? sampling frequency: f s = 32768 hz/15 = 2184.53 hz. ? f 0 is the fundamental frequency of the mains phases . ? imax is the external rms current corresponding to 250 mv pk at each iadc input . ? vmax is the external rms voltage corresponding to 250 mv pk at each vadc input. ? n acc , the accumulation count for energy measurements is sum_samp s [12:0] (i/o ram 0x2107[4:0], 0x2108[7:0]) . this value also resides in sum_pre ( ce ram 0x23 ) where it is used for phase angle measurement. ? the duration of the accumulation interval for energy measurements is sum_samps[12:0] /f s . ? x is a gain constant of the pulse generators. its value is determined by pulse_fast and pulse_slow (see table 68 ) . ? voltage lsb = vmax * 7.879810 - 9 v. ? vmax = 600 v, imax = 208 a, and kh = 3.2 wh/pulse are assumed as default s ettings. the system constants imax and vmax are used by the mpu to convert internal digital quantities (as used by the ce) to external, i.e. metering quantities. their values are determined by the scaling of the voltage and current sensors used in an actual meter. the lsb values used in this document relate digital quantities at the ce or mpu interface to external meter input quantities. for example, if a sag threshold of 80 v peak is desired at the meter input, the digital value that should be program med into sag_thr (ce ram 0x24) would be 80 v/ sag_thr lsb , where sag_thr lsb is the lsb value in the description of sag_thr ( table 69 ) . the parameters equ[2:0] , ce_e, and sum_samps[12:0] , essential to the function of the ce are stored in i/o ram (see 5.2 for details ). downloaded from: http:///
71m6545/71M6545H data sheet v2 101 5.4.4 environment before starting the ce using the ce_e bit ( i/o ram 0x2106[0]) , the mpu has to establish the proper envi ronment for the ce by implementing the following steps: ? locate the ce code in flash memory using ce_lctn[5:0] ( i/o ram 0x2109[5:0] ) ? load the ce data into ram. ? establish the equation to be applied in equ[2:0] (i/o ram 0x2106[7:5]) . ? establish the accumulation period and number of samples in sum_samps[12:0] (i/o ram 0x2107[4:0], 0x2108[7:0]) . ? establish the number of cycles per adc multiplexer frame ( mux_div[3:0] (i/o ram 0x2100[7:4]) ). ? apply proper values to muxn_sel , as well as proper selections for diffn_e ( i/o ram 0x210c[ ]) and rmtn_e ( i/o ram 0x2709[ ] in order to configure the analog inputs. ? initialize any mpu interrupts, such as ce_busy, xfer_busy, or the power - failure detection interrupt. when different ce codes are used, a different set of environment parameters need to be established. the exact values for these parameters are listed in the application notes and other documentation which accompanies the ce code. operating ce codes with environment parameters deviating from the val ues specified by maxim lead s to unpredictable results. typically, there are fifteen 32768 hz cycles per adc multiplexer frame (see 2.2.2 ). t his means that the product of the number of cycles per frame and the number of conversions per frame must be 14 (allowing for one settling cycle). the default configuration is fir_len = 01 , i/o ram 0x210c[1] (two cycles per conversion) and mux_div[3:0] = 7 (7 conversions per multiplexer cycle). sample configurations can be copied from demo code provided by maxim with the demo kits. 5.4.5 ce calculations referring to table 63 , the mpu selects the desired equation by writing the equ[2:0] ( i/o ram 0x2106[7:5] ). table 63 : ce equ[2:0] equations and element input mapping equ [2:0] * watt & var formula ( wsum/varsum ) w0sum/ var0sum w1sum/ var1sum w2sum/ var2sum i0sq sum i1sq sum i2sq sum 2 va*ia + vb*ib (2- element, 3 - w, 3 delta ) va * ia vb * ib n/a ia ib C 3 va*(ia - ib)/2 + vc*ic (2 element, 4w 3 delta) va*(ia - ib)/2 C vc*ic ia - ib ib ic 4 va*(ia - ib)/2 + vb*(ic - ib)/2 (2 element, 4w 3 wye) va*(ia - ib)/2 vb*(ic - ib)/2 C ia - ib ic - ib ic 5 va*ia + vb*ib + vc*ic (3 element, 4w 3 wye) va*ia vb*ib vc*ic ia ib ic note: * only equ[2:0] = 5 is supported by the currently available ce code versions for the 71m6545/h . contact your local maxim representative for ce codes that support equations 2, 3 and 4. downloaded from: http:///
71m6545/71M6545H data sheet 102 v2 5.4.6 ce front end data (raw data) access to the raw data provided by the afe is possible by reading ce ram addresses 0 through a , as shown in table 64 . in the expression mux n _s el [3:0] = x, n refers to the multiplexer frame time slot number and x refers to the desired adc input number or adc handle (i. e., iadc0 to vadc10 , or simply 0 to 10 decimal). the 71m6545/h can support up to eleven sensor inputs, when all the current sensors are configured as single - ended inputs. if all the current sensor inputs are configured as diff erential (recommended for best performance), the number of input sensor channels is reduced to se ven (i.e., ia dc0 -1 , i adc2 -3 , i adc4 -5 , i adc6 -7 , va dc8 , v adc9 and v adc10 ). the mux n _sel [3:0] column in table 64 shows the mux n _sel handles for the various sensor input pins. for ex ample, if differential mode is enable d via control bit diff0 _e = 1 ( i/o ram 0x210c[4] ), then the iadc0 - iadc1 input pins a re combined together to form a single differential input and the corresponding mux n _sel handle is 0 (i.e., handle 1 is then unused) . similarly, the ce ram location column provides the ce ram address where the corresponding sample data is stored. continuing with the same example, if diff0 _e = 1, the corresponding ce ram location where the samples for the iadc0 - iadc1 differential input are stored is ce ram 0. the iadc2 -3 , i adc4 -5 and i adc6 -7 input s can be configured as direc t- connected sensor s (i.e., directly connected to the 71m6545/h ) or as remote sensor s (i.e., using a 71m6xx 3 isolated sensor). for example, i f the iadc2 -3 remote sensor is disabled by rmt2 _e = 0 ( i/o ram 0x2007[3] ) and differential mode is enabled by diff2 _e = 1 ( i/o ram 0x210c[4] ) , then iadc2 - iadc3 form a differential input with a mux n _sel handle of 2 (i.e., handle 3 is then unused), and the corresponding samples are stored in ce ram location 2. if the remote sensor enable bit rmt2 _e = 1 , diff2 _e = x (do nt care) , then the mux n _sel handle is not required (i.e., the sensor is not connected to the 71m6545/h multiplexer , so mux n _sel does not apply), and the samples corresponding to this remote differential iadc2 - iadc3 input are stored in ce ram location 2 directly by the digital isolation interface (see figure 2 ). the voltage sensor inputs (va dc8 , v adc9 and v adc10 ) are always single - ended inputs and cannot be configured as remotes, so they do not have any associated configuration bits. vadc8 ( va ) has a mux n _sel handle value of 8 , and its samples are stored in ce ram location 8 . vadc9 ( vb ) has a mux n _sel han dle value of 9 and its samples are stored in ce ram location 9. vadc10 ( vc ) has a mux n _sel han dle value of 10 and its samples are stored in ce ram location 10. table 64 : ce raw data access locations pin muxn_sel handle ce ram locati on diff0 _e diff0 _e 0 1 0 1 iadc0 0 0 0 0 iadc1 1 1 rmt2 _e, diff2 _e rmt2 _e, diff2 _e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc2 2 2 - - 2 2 2* 2* iadc3 3 3 rmt4 _e, diff4 _e rmt4 _e, diff4 _e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc4 4 4 - - 4 4 4* 4* iadc5 5 5 rmt6 _e, diff6 _e rmt6 _e, diff6 _e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc6 6 6 - - 6 6 6* 6* iadc7 7 7 there are no configuration bits for vadc8 , 9, 10 vadc8 (va) 8 8 vadc9 (vb) 9 9 vadc10 (vc) 10 10 *remote interface data downloaded from: http:///
71m6545/71M6545H data sheet v2 103 5.4.7 ce s tatus and control the ce status word is useful for generating early warnings to the m pu ( table 65 ) . it contains sag warnings for phase a, b, and c, as well as f0 , the derived clock operating at the fundamental input frequency. the mpu can read the ce status word at every ce_busy interrupt. since the ce_busy inter rupt occurs at the sample rate (i.e . , 2520.6 hz for mux_div[3:0] =6 or 2184.5 hz for mux_div[3:0] =7) , it is desirable to minimize the computation required in the interrupt handler of the mpu . table 65 : cestatus register ce address name description 0x80 cestatus see description of cestatus bits in table 66 . cestatus provides information about the status of voltage and input ac signal frequency, which are useful for generating an early power fail warning to initiate necessary data storage. c estatus re pre sents the status flags for the preceding ce code pass (ce_busy interrupt). the significance of the bits in cestatus is shown in table 66 . table 66 : cestatus bit definitions cestatus bit name description 31: 4 not used these unused bits are always zero. 3 f0 f0 is a square wave at the exact fundamental input frequency. 2 sag_ c normally zero. becomes one when vadc10 (vc) remains below sag_thr (ce ram 0x24) for sagcnt samples. does not return to zero until vadc10 (vc) rises above sag_thr . 1 sag_b normally zero . becomes one when vadc9 (vb) remains below sag_thr for sag_cnt samples . does not return to zero until vadc9 (vb) rises above sag_thr . 0 sag_a normally zero . becomes one when vadc8 (va) remains below sag_thr for sag_cnt samples . does not return to zero until vadc8 (va) rises above sag_thr . the ce is initialized by the mpu using ceconfig ( table 67 ). t his register contains in packed form sag_cnt, freqsel 0 , freqsel 1, ext_pulse, pulse_slow, and pulse_fast . the ceconfig bit definitions are given in table 68 . table 67 : ceconfig register ce address name data description 0x20 ceconfig 0x0030da20 see description of the ceconfig bits in table 68 . the ext_temp bit enables temperature compensation by the mpu, when set to 1. when 0, internal (ce) temperature compensation is enabled. the ce pulse generator can be controlled by either the mpu (exter nal) or ce (internal) variables . control is by the mpu if ext _ pul se = 1 . in this case, the mpu controls the pulse rate by placing values into apulsew and apulser (ce ram 0x44 and 0x48) . by setting ext _ pulse = 0, the ce controls the pulse rate based on wsum_x (ce ram 0x84) and varsum_x (ce ram 0x88). the 71m6545/h demo code creep function halts both internal and external pulse generation. downloaded from: http:///
71m6545/71M6545H data sheet 104 v2 table 68 : ceconfig bit definitions (ce ram 0x20) ceconfig bit name default description 23 reserved 0 reserved (can be used by the mpu to indicate that the 71m6x03 is being used; ce does not use this). 22 ext_temp 0 when 1, the mpu controls temperature compensation via the gain_adjn ( ce ram 0x40 - 0x42 ) , when 0, the ce is in control. 21 edg e_int 1 when 1, xpulse produces a pulse for each zero - crossing of the mains phase selected by freqsel[1:0] , which can be used to interrupt the mpu. 20 sag_int 1 when 1, activates the ypulse/dio 7 output when a sag is detected on the phase selected with freq sel[1 :0] . 19: 8 sag_cnt 218 (0xda ) the number of consecutive voltage samples below sag_thr ( ce ram 0x24 ) before a sag alarm is declared. the default value is equivalent to 1 0 0 ms . 7 :6 freqsel[1:0] 0 freqsel[1 :0] selects the phase to be used for the frequency monitor, sag detection, the phase - to - phase lag calculation and for the zero crossing counter ( mainedge_x , ce ram 0x83 ). fr e q sel [1:0] phase se lected phases selected ph_atob_x ph_a to c _x 0 0 a a-b a-c 0 1 b b-c b-a 1 0 c c-a c-b 1 1 not allowed 5 ext_pulse 1 when zero, causes the pulse generat o rs to respond to internal data. wpulse = wsum_x ( ce ram 0x84) , vpulse = varsum_x (ce ram 0x88.) otherwise, the generators respond to values the mpu places in apulsew and apulser (ce ram 0x44 and 0x48) 4 :2 reserved 0 reserved. 1 pulse_fast 0 when pulse_fast = 1, the pulse generator input is increased 16x . when pulse_slow = 1, the pulse generator input is re duced by a factor of 64. these two parameters control the pulse gain factor x (see table below). allowed values are e i ther 1 or 0. default is 0 for both (x = 6). pulse_ fast pulse_ slo w x 0 0 1.5 * 2 2 = 6 0 1 1.5 * 2 -4 = 0.09375 1 0 1.5 * 2 6 = 96 1 1 do not use 0 pulse_slow 0 the freqsel[1:0] field in ceconfig ( ce ram 0x20[7:6] ) selects the ph ase that is utilized to generate a sag interrupt . thus, a sag_int event occurs when the selected phase has satisfied the sag event criteria as set by the sag_thr ( ce ram 0x24 ) register and the sag_cnt field in ceconfig (ce ram 0x20[19:8]). when the sag_int bit ( ce ram 0x20[20] ) is set to 1, a sag event generates a tran sition on the ypulse output. after a sag interrupt, the mpu should change the freqsel[1:0] setting to select the other phase, if it is powered. even though a sag interrupt is only generated on the selected phas e, all three phases are simultaneously checked for sag. the presence of power on a given phase can be sensed by directly checking the sag_a , sag_b and sag_c bits in cestatus ( ce ram 0x80[0:1]). the ext_temp bit enables temperature compensation by the mpu, when set to 1. when 0, internal (ce) temper ature compensation is enabled. downloaded from: http:///
71m6545/71M6545H data sheet v2 105 the ce pulse generator can be controlled by either the mpu (exter nal) or ce (internal) variables. control is by the mpu if the ext _ pulse bit = 1 ( ce ram 0x20[5] ) . in this case, the mpu controls the pulse rate (external pulse generation) by placing values into apulsew and apulser (ce ram 0x4 5 and 0x4 9) . by setting ext _ pulse = 0, the ce controls the pulse rate based on wsum_x (ce ram 0x84) and varsum_x (ce ram 0x88). table 69 : sag threshold , phase measurement, and gain adjust control ce address name default description 0x24 sag_thr 2.39*10 7 the voltage threshold for sag warnings. the default value is equivalent to 80 v rms if vmax = 600 v. sag_thr = ? ??? ? 2 ???? ?7 . 8798?10 ?9 0x40 gain_adj0 16384 the assignments of these gain adjustments depends on the meter design. see 4.5.5 temperature compensation for vref and shunt sensors on page 75 or 4.5.6 temperature compensation of vref and current transformers on page 77 . the default value of 16384 corresponds to unity gain. 0x41 gain_adj1 16384 0x42 gain_adj2 16384 0x43 gain_adj3 16384 0x44 gain_adj4 16384 5.4.8 ce transfer v ariables when the mpu receives the xfer_busy interrupt, it knows that fresh d ata is available in the transfer variables . ce trans fer variables are modified during the ce code pass that ends with an xfer_bu sy interrupt. they remain constant throughout each accumulation interva l. in this data sheet, the names of ce transfer variables always end with _x. the transfer variables can be categorized as: ? fundamental energy measurement variables ? instantaneous (rms) values ? other measurement parameters fundamental energy measurement v ariables table 70 describes each transfer variable for fundamental energy measurement . all variables are signed 32 - bit integers . accumulated variables such as wsum are internally scaled so they have at least 2x margin before overflow when the integration time is one second . additionally, the hardware does not permit output values to fold back upon overflow . table 70 : ce transfer variables (with shunts) ce address name description configuration 0x84 wsum_x the signed sum: w0sum_x+w1sum_x+w2sum_x . figure 27 (page 72 ) 0x85 w0sum_x the sum of wh samples from each wattmeter element . lsb w = 7.7562 *10 -13 vmax * imax wh. 0x86 w1sum_x 0x87 w2sum_x 0x88 varsum_x the signed sum: var0sum_x+var1sum_x+var2sum_x. 0x89 var0sum_x the sum of var h samples from each wattmeter element . lsb w = 7.7562 *10 -13 vmax * imax var h. 0x8a var1sum_x 0x8b var2sum_x downloaded from: http:///
71m6545/71M6545H data sheet 106 v2 table 71 : ce transfer variables (with cts) ce address name description configuration 0x84 wsum_x the signed sum: w0sum_x+w1sum_x+w2sum_x . figure 28 (page 73 ) 0x85 w0sum_x the sum of wh samples from each wattmeter element . lsb w = 1.0856 *10 -12 vmax imax wh. 0x86 w1sum_x 0x87 w2sum_x 0x88 varsum_x the signed sum: var0sum_x+var1sum_x+var2sum_x. 0x89 var0sum_x the sum of var h samples from each wattmeter element . lsb w = 1.0856 *10 -12 vmax imax var h. 0x8a var1sum_x 0x8b var2sum_x w sum_x and varsum_x are the signed sum of phase - a, phase - b and phase - c wh or varh values ac cording to the metering equation specified in the control field equ[2:0] (i/o ram 0x2106[7:5]) . wn sum_x is the wh value accumulated for phase n in the last accumulation interval and can be computed based on the specified lsb value. for examp le , with vmax = 600 v and imax = 208 a, the lsb for wn sum_x is 0. 135 wh. 5.4.8.1 instantaneous energy measurement variables in sqsum_x and vn sqsum are the squared current and voltage samples acquired during the last accumulation interval. insqsum_x can be used for computing the neutral current. table 72 : ce energy measurement variables (with shunts) ce address name description configuration 0x8c i0sqsum_x neutral current: lsb i = 9.9045*10 - 13 * imax 2 a 2 h ( pre_e =0) lsb i = 6.1903125*10 - 14 * imax 2 a 2 h ( pre_e =1) figure 27 (page 72 ) 0x8d i1sqsum_x lsb i = 6.3968*10 - 13 * (imax 2 ) a 2 h 0x8e i2sqsum_x 0x8f i3sqsum_x 0x90 v0sqsum_x lsb v = 9.4045*10 - 13 *vmax 2 v 2 h 0x91 v1sqsum_x 0x92 v2sqsum_x tabl e 73 : ce energy measurement variables (with cts) ce address name description configuration 0x8c i0sqsum_x lsb i = 1.0856 *10 -12 * ( imax 2 ) a 2 h figure 28 (page 73 ) 0x8d i1sqsum_x 0x8e i2sqsum_x 0x8f i3sqsum_x 0x90 v0sqsum_x lsb v = 1.0856 *10 -12 * vmax 2 v 2 h 0x91 v1sqsum_x 0x92 v2sqsum_x downloaded from: http:///
71m6545/71M6545H data sheet v2 107 the rms values can be computed by the mpu from the squared current and voltage samples as follows: other t ransfer variables include those available for frequency and phase measurement, and those r e flecting the count of the zero - crossings of the mains voltage and the battery voltage. these transfer variables are listed in table 74 . mainedge_x reflects the number of half - cycles accounted for in the last accumulated interval for the ac signal of the phase specified in the freqsel [1 :0] field of the ceconfig register ( ce ram 0x20[7:6] ) . mainedge_x is useful for implementing a real - time clock based on the input ac signal. table 74 : other transfer variables ce address name description 0x82 freq_x fundamental frequency : lsb 6 32 10 509 .0 2 2184 ? ? hz hz (for ct) lsb 6 32 10 587 .0 2 2520 ? ? hz hz (for shunt) 0x83 mainedge_x the number of edge crossings of the selected voltage in the pre vious ac cumulation interval. edge crossings are either direction and are de - bounced . 0x94 ph_atob_x voltage phase lag. the selection of the reference phase is based on freqsel[1: 0] in the cec onfig register: if freqsel[1 :0] se lect s phase a: phase lag from a to b. if freqsel[1 :0] select s phase b: phase lag from b to c. if freqsel[1 :0] select s phase c: phase lag from c to a. a ngle in degrees is (0 to 360): ph_atob_x * 360/n acc + 2.4 *15/13 (for ct) a ngle in degrees is (0 to 360): ph_atob_x * 360/n acc + 2.4 (for shunt) 0x95 ph_atoc_x if freqsel[1 :0] select s phase a: phase lag from a to c. if freqsel[1 :0] select s phase b: phase lag from b to a. if freqsel[1 :0] select s phase c: phase lag from c to b. angle in degrees is (0 to 360): ph_atoc _x * 360/n acc + 4.8*15/13 (for ct) angle in degrees is (0 to 360): ph_atoc _x * 360/n acc + 4.8*15/13 (for shunt) phase angle measurement accuracy can be increased by writing values > 1 into v_ang_cnt ( v_ang_cnt indicates how many accumulation periods to sum ph_atob_x and ph_atoc_x over. the mpu then has to divide by that number. for standard ce codes that s upport shunts with remotes, v_ang_cnt is at ce address 0x53. for standard ce codes that support shunts with ct, v_ang_cnt is at ce address 0x55. for other than standard ce codes, contact maxim for information). 5.4.9 pulse generation table 75 describes the ce pulse generation parameters . the combination of the ceconfig pulse_slow (ce ram 0x20[0] ) and pulse_fast (ce ram 0x20[1] ) bits control s the speed of the pulse rate. the default values of 0 and 0 maintain the original pulse rate given by the kh equation. wrate ( ce ram 0x21 ) controls the number of pulses that are generated per measured wh and varh quantities. the lower wrate is the slower the pulse rate for measured energy quantity. the metering con stant kh is derived from wrate as the amount of energy measured for each pulse. that is, if kh = acc s i rms n f lsb ixsqsum ix ? ? ? = 3600 acc s v rms n f lsb vxsqsum vx ? ? ? = 3600 downloaded from: http:///
71m6545/71M6545H data sheet 108 v2 1wh/pulse, a power applied to the meter of 120 v and 30 a results in one pulse pe r se cond. if the load is 240 v at 150 a, ten pulses per second are generated. control is transferred to the mpu for pulse generation if ext_pulse = 1 (ce ram 0x20[5]) . in this case, the pulse rate is de termined by apulsew and a pulser (ce ram 0x44 and 0x 48) . the mpu has to load the source for pulse generation in apulsew and apulser to generate pulses. irrespective of the ext_pulse status , the output pulse rate controlled by apulsew and apulser is implemented by the ce only. by setting ext_pulse = 1 , the mpu is providing the source for pulse generation. if ext_pulse is 0 , w0sum_x and var0sum_x are the default pulse generation sources. in this case, creep cannot be con trolled since it is an mpu function. the maximum pulse rate is 3*f s = 7.5 khz . see 2.3.6.2 vpulse and wpulse (page 27 ) for details on how to adjust the timing of the output pulses. the maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67 s) and is independent of the number of pulses measured. thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. after 10 seconds, the peak jitter is 6.7 ppm. the average jitter is always zero. if it is attempted to drive either pulse generator faster than its maximum rate, it simply output s at its maximum rate without exhibiting any rollover characteristics. the actual pulse rate, using wsum as an example, is: hz x f wsum wrate rate s 46 2 ? ? ? = , where f s = sampling frequency (2184 . 53 hz), x = pulse speed factor derived from the ce variables pulse_slow (ce ram 0x20[0]) and pulse_fast (ce ram 0x20[ 1 ]) . table 75 : ce pulse generation parameters ce address name default description 0x21 wrate 227 kh = vmax*imax* k / ( wrate *n acc *x) wh/pulse where: k = 76.3594 when used with local sensors (ct or shunt) k = 54.5793 when used with 71m6xx3 remote sensors 0x22 kvar 6444 scale factor for var measurement. 0x23 sum_pre 2184 number of samples per accumulation interval, as specified in sum_samps[12:0], i/o ram 0x2107[4:0], 0x2108[7:0] (n acc ). 0x45 apulsew 0 wh pulse (wpulse) generator input to be updated by the mpu when using external pulse generation. the output pulse rate is: apulsew * f s * 2 - 32 * wrate * x * 2 - 14 . thi s input is buffered and can be updated by the mpu during a conversion interval. the change take s effect at the beginning of the next interval. 0x46 wpulse_ctr 0 counter for wpulse output. 0x47 wpulse_ frac 0 unsigned numerator, containing a fraction of a pulse. the value in this register always counts up towards the next pulse. 0x48 wsum_ accum 0 roll - over accumulator for wpulse. 0x49 apulser 0 var h (vpulse) pulse generator input . 0x4a vpulse_ctr 0 counter for vpulse output. 0x4b vpulse_ frac 0 unsigned numerator, containing a fraction of a pulse. the value in this register always count s up towards the next pulse. 0x4c vsum_accum 0 roll - over accumulator for vpulse. downloaded from: http:///
71m6545/71M6545H data sheet v2 109 other ce parameters table 76 shows the quant ce parameters used for suppression of noise due to scaling and truncation effects. the equations for calculating the lsb weight of each quant parameter are provi ded at the bot tom of table 76 . table 76 : ce parameters for noise suppression and code version ce address name default description 0x2 6 quant _ia 0 compensation factors for truncation and noise in current, real energy and reactive energy for phase a. 0x27 quant_wa 0 0x28 quant_ vara 0 0x2 a quant _ib 0 compensation factors for truncation and noise in current, real energy and reactive energy for phase b. 0x2b quant_wb 0 0x2c quant_varb 0 0x2 e quant _ic 0 compensation factors for truncation and noise in current, real energy and reactive energy for phase c. 0x2f quant_wc 0 0x30 quant_varc 0 0x31 quant_id 0 compensation factors for truncation and noise in current for phase d. lsb weights for use with the 71m6xx3 isolated sensors : ) ( 10 20864 .5 _ _ 2 2 10 amps imax lsb ix quant ? ? = ? ) ( 10 59147 .8 _ _ 10 watts imax vmax lsb wx quant ? ? ? = ? ) ( 10 59147 .8 _ _ 10 vars imax vmax lsb varx quant ? ? ? = ? lsb weights for use with current transformers (cts): ) ( 10 08656 .5 _ _ 2 2 13 amps imax lsb ix quant ? ? = ? ) ( 10 04173 .1 _ _ 9 watts imax vmax lsb wx quant ? ? ? = ? ) ( 10 04173 .1 _ _ 9 vars imax vmax lsb varx quant ? ? ? = ? downloaded from: http:///
71m6545/71M6545H data sheet 110 v2 5.4.10 ce calibration parameters table 77 lists the parameters that are typically entered to effect calibration of me ter accuracy. table 77 : ce calibration parameters ce address name defau lt description 0x10 cal_ia 16384 these constants control the gain of their respective channels. the n ominal value for each parameter is 2 14 = 16384. the gain of each channel is directly proportional to its cal parameter. thus, if the gain of a channel is 1% low, cal should be increased by 1%. 0x11 cal_va 16384 0x13 cal_ib 16384 0x14 cal_vb 16384 0x16 cal_ic 16384 0x17 cal_vc 16384 0x19 cal_i d 16384 0x1 2 phadj_a 0 these constants control the ct phase compensation. no com pensation occurs when phadj_x = 0. as phadj_x is increased, more compensation (lag) is introduced. the r ange is 2 15 C 1. if it is desired to delay the current by the angle , the equations are : ? ? = tan tan x phadj 0168 .0 1714 .0 029615 .0 2 _ 20 at 60hz ? ? ? = tan tan x phadj 01226 .0 1430 .0 0206 .0 2 _ 20 at 50hz 0x1 5 phadj_b 0 0x1 8 phadj_c 0 0x12 dlyadj_a 0 the shunt delay compensation is obtained using the equation provided below: ( ) ? ?? ? ? ?? ? + ? ?? ? ? ?? ? + ? ?? ? ? ?? ? ? + ?= s s s rees rees f f c b f f ab f f a x dlyadj 2 sin 2 cos 2 2 cos 360 2 2 1.0 1 _ 2 2 14 deg deg where: a a 2 = 1 2 + = a b 2 2 cos 4 2 2 + ? ?? ? ? ?? ? + = s f f a a c the table below provides the value of a for each channel: channel value of a (decimal) dlyadj_a 13840 dlyadj_ b 11693 dlyadj_ c 9359 f is the mains frequency. f s is the sampling frequency. 0x15 dlyadj_b 0 0x18 dlyadj_c 0 note: the current sensor inputs are not assigned to the a, b and c phases in a fixed manner. the assignments of phases a, b and c depends on how the iadc0 - 1, iadc2 - 3, iadc4 - 5, iadc6 - 7 current sensing inputs are connected in the meter design. the ce code must be aware of these connections. see figure 27 and figure 28 for typical meter configurations. vadc8, vadc9 and vadc10 are assigned to voltage phases va, vb and vc in a fixed manner, respectively. the ce addresses listed in this table are assigned to phases a, b , and c as indicated by their names. downloaded from: http:///
71m6545/71M6545H data sheet v2 111 5.4.11 ce flow diagrams figure 34 through figure 36 show the data flow through the ce in simplified form. func tions not shown include delay compensation, sample interpolation, scaling and the processing of met er equations. figure 34 : ce data flow: multiplexer and adc figure 35 : ce data flow: scaling, gain control, intermediate v ariables for one phase vref multiplexer f s = 2184 hz ? mod deci - mator de - multiplexer f s = 2184 hz ia_raw ia vb va ib ic vc ib_raw va_raw vb_raw ic_raw vc_raw i d i d _raw downloaded from: http:///
71m6545/71M6545H data sheet 112 v2 figure 36 : ce data flow: squaring and summation stages v ia wa square wb vara varb va iasq vasq ibsq sum iasqsum_x vasqsum_x icsqsum_x sum wasum_x wbsum_x varasum_x varbsum_x sum_samps = 2184 mpu f0 i 2 v 2 wc varc wcsum_x varcsum_x ibic vb vc icsq vbsq vcsq ibsqsum_x vbsqsum_x vcsqsum_x f0 id idsq idsqsum_x downloaded from: http:///
71m6545/71M6545H data sheet v2 113 6 71m6545/h s pecifications this section provides the electrical specifications for the 71m6545/h . please refer to the 71m6xxx data sheet for the 71m6xx3 electrical specifications, pin - out and package mechanical data. 6.1 a bsolute m aximum r atings table 78 shows the absolute maximum ranges for the device. stresses beyond absolute maxi mum ratings may cause permanent damage to the device. these are stress ratings only and functional operation a t these or any other conditions beyond those indicated under recommended operating conditi ons ( see 6.3 ) is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. all voltages are with respect to gnda. table 78 : a bsolute maximum ratings voltage and current supplies and ground pins v3p3sys, v3p3a ? 0.5 v to + 4.6 v vbat_rtc - 0.5 v to + 4.6 v gndd - 0.1 v to +0.1 v analog output pins vref - 10 ma to +10 ma, - 0.5 v to v3p3a+0.5 v vdd - 10 ma to +10 ma, - 0.5 to +3.0 v v3p3d - 10 ma to + 10 ma, - 0.5 v to + 4.6 v analog input pins i adc0 , i adc1 , i adc2 , i adc3 , i adc4 , i adc5 , i adc6 , i adc7, vadc8, v adc9 and v adc10 - 10 ma to +10 ma - 0.5 v to v3p3a+0.5 v xin, xout - 10 ma to +10 ma - 0.5 v to + 3.0 v dio pins configured as digital inputs - 10 ma to + 10 ma, - 0.5 v to + 6 v configured as digital outputs - 10 ma to + 10 ma, - 0.5 v to v3p3d+0.5 v digital pins inputs (pb, reset, rx, ice_e, test) - 10 ma to + 10 ma, - 0.5 to 6 v outputs (tx) - 10 ma to + 10 ma, - 0.5 v to v3p3d+0.5 v temperature and esd stress operating junction temperature (peak, 100ms) 140 c operating junction temperature (continuous) 125 c storage temperature ? 45 c to +165 c solder temperature C 10 second duration 250 c downloaded from: http:///
71m6545/71M6545H data sheet 114 v2 6.2 recommended external components table 79 : recommended external components name from to function value unit c1 v3p3a gnda bypass capacitor for 3.3 v supply 0.1 20% f c2 v3p3d gndd bypass capacitor for 3.3 v output 0.1 20% f csys v3p3sys gndd bypass capacitor for v3p3sys 1.0 30% f cvdd vdd gndd bypass capacitor for v dd 0.1 20% f xtal xin xout 32.768 khz crystal C electrically equivalent to ecs .327 - 12.5 - 17x or vishay xt26t, load capacitance 12.5 pf 32.768 khz cxs xin gnda load capacitor values for crystal de pend on crystal spec ification s and board parasit ics . nominal values are based on 4 pf board capacitance and include an allowance for chip capacitance. 15 10% pf cxl xout gnda 10 10% pf 6.3 r ecommended operating c onditions unless otherwise specified, all parameters listed under 6.4 performance specifications and 6.5 timing specifications are valid over the recommended operating conditions provided in table 80 below. table 80 : recommended operating conditions parameter condition min typ max unit v3p3sys and v3p3a supply voltage for precision metering operation (msn mode). voltage at vbat_rtc need not be present. vbat_rtc =0 v to 3.8 v 3.0 3.6 v vbat_rtc voltage. vbat_rtc is not needed to support the rtc and non - volatile memory unless v3p3sys<2.0 v v3p3sys<2.0 v 2.0 3.8 v operating temperature - 40 +85 oc notes: 1. gnda and gndd must be connected together. 2. v3p3sys and v3p3a m u st be connected together. downloaded from: http:///
71m6545/71M6545H data sheet v2 115 6.4 p erformance s pecifications 6.4.1 input logic levels table 81 : i nput logic levels parameter condition min typ max unit digital high - level input voltage, v ih 2 v digital low - level input voltage, v il 0.8 v input pull - up current, i il e_rxtx, e_rst, e_tclk spi_csz (dio36) other digital inputs vin=0 v , ice_e= 3.3 v 10 10 -1 0 100 100 1 a a a input pull down current, i ih ice_e, reset, test other digital inputs vin=v3p3d 10 -1 0 100 1 a a 6.4.2 o utput logic levels table 82 : output logic levels parameter condition min typ max unit digital high - level output voltage v oh i load = 1 ma v3p3d C 0.4 v i load = 15 ma (see notes 1, 2) v3p3d - 0.6 v digital low - level output voltage v ol i load = 1 ma 0 0.4 v i load = 15 ma (see note 1) 0 0.8 v note: 1. guaranteed by design; not production tested. 2. caution: the sum of all pull up currents must be compatible with the on - resistance of the internal v3p3d switch. see 6.4.6 v3p3d switch on page 117 . 6.4.3 battery monitor table 83 : batter y monitor performance specifications ( temp_bat = 1) parameter condition min typ max unit bv: battery voltage (definition) msn mode, temp_pwr = 1 ?? = 3.3 ? + ( ?????? ? 142 ) ? 0. 0246 ? + ????? ? 297 ?? v measurement error ? ?? ? ? ?? ? ? ? 1 _ 100 rtc vbat bv vbat _rtc = 2.0 v 2.5 v 3.0 v 4.0 v - 7.5 -5 -3 -3 7.5 5 3 5 % % % % input impedance in continuous measurement, msn mode. v(vbat_rtc)/i(vbat_rtc) v3p3 = 3.3 v, 0x28a0[7] = 0, temp_per = 111, vbat_rtc = 3.6 v, 1 m? load applied with bcurr ibat( bcurr =1) - ibat( bcurr =0) v3p3 = 3.3 v 50 100 140 a downloaded from: http:///
71m6545/71M6545H data sheet 116 v2 6.4.4 temperature monitor table 84 . temperature monitor parameter condition min typ max unit temperature measurement equation for 71m6545 (see notes 2 and 4) in msn, temp_pwr =1: ???? = 0. 325 ? ????? + 22 c temperature measurement equation for 71M6545H (see notes 3 and 4) in msn, temp_pwr =1: if stemp 0: ???? = 0. 325 ? ????? + 22 if stemp > 0: ???? = 63 ? ????? ???? _ 85 + 22 temperature error (71m654 5/h ) t a = 22 ? c -2 2 c vbat_rtc charge per measurement 0x28a0[7] = 0, temp_pwr =0, slp mode, vbat_rtc = 3.6 v 16 c duration of temperature measurement after setting temp_start (see note 1) 15 60 ms note s: 1. guaranteed by design; not production tested. 2. for the 71m6545, temp_85 fuses read 0. 3. for the 71M6545H, temp_85 fuses 0. 4. the coefficients provided in these equations are typical. downloaded from: http:///
71m6545/71M6545H data sheet v2 117 6.4.5 s upply c urrent the supply currents provided in below in table 85 include only the current consumed by the 71m6545/h. refer to the 71m6xxx data sheet for additional current required when using a 71m6x03 remote sensor. table 85 : supply current performance specifications parameter condition min typ max unit i1a: v3p3a + v3p3sys current, normal operation polyphase: 4 currents, 3 voltages v3p3a = v3p3sys = 3.3 v, mpu_div [2:0] = 3 (614 khz mpu clock), no flash memory write, rtm_e =0, pre_e =0, ce_e =1, adc_e =1, adc_div =0, mux_div[3:0] =7, fir_len[1:0] =1, pll_fast =1 7.2 8.5 ma i1b: v3p3a + v3p3sys current, normal operation pll_fast =0 same as i1a, except pll_fast =0 2.9 3.8 ma i1c: v3p3a + v3p3sys current, normal operation pre_e =1 same as i1a, except pre_e =1 7.3 8.7 ma i1d: v3p3a + v3p3sys current, normal operation pre_e =1, adc_div =1, fir_len =0. (see note 1) same as i1a, except pre_e =1, adc_div =1, fir_len =0. 6.5 7.5 ma i1e: v3p3a + v3p3sys current, normal operation pll_fast =0, pre_e =1. (see note 1) same as i1a, except pre_e =1, pll_fast =0. 3.0 3.9 ma i2: v3p3a + v3p3sys dynamic current same as i1 a , except with varia tion of mpu_div[2:0] . 4.3 i- i 3 mpu_div 0 mpu_div = = 0.4 0.6 ma/ mhz vbat_rtc current i3a : msn i3b : slp mode i3c : slp mode (see note 1) t a 25 c t a = 85 c -300 0 0.7 1.5 300 1.7 3.2 na a a i4: v3p3a + v3p3sys current, write flash with ice same as i1, except write flash at maximum rate, ce_e =0, adc_e =0. 7.1 8.7 ma note: 1. guaranteed by design; not production tested. 6.4.6 v3p3d s witch table 86 : v3p3d switch performance specifications p arameter condition m in t yp max unit on resistance C v3p3sys to v3p3d | i v3p3d | 1 ma 10 v3p3d i oh , msn v3p3sys = 3v v3p3d = 2.9v 10 ma downloaded from: http:///
71m6545/71M6545H data sheet 118 v2 6.4.7 internal power fault comparators p arameter condition m in t yp max unit overall response time 100mv overdrive, falling 100mv overdrive, rising 20 200 200 s s falling threshold 3.0 v comparator 2.8 v comparator difference 3.0v and 2.8v comparators v3p3 falling 2.83 2.75 50 2.93 2.81 136 3.03 2.87 220 v v mv falling threshold 2.25 v comparator 2.0 v comparator difference 2.25v and 2.0v comparators vdd falling 2.2 1.9 0 0.15 2.25 2.00 0.25 2.5 2.20 0.35 v v v hysteresis, (r ising threshold - f alling threshold ) 3.0 v comparator 2.8 v comparator 2.25 v comparator 2.0 v comparator t a = 22 c 22 25 10 10 45 42 33 28 65 60 60 60 mv mv mv mv 6.4.8 2.5 v v oltage r egulator C system power table 87 : 2.5 v voltage regulator performance specifications (vdd pin) p arameter condition m in t yp max unit v2p5 v3p3 = 3.0 v - 3.8 v i load = 0 ma 2.55 2. 65 2.7 5 v v2p5 load regulation v3p3 = 3.3 v i load = 0 ma to 5 ma 40 mv voltage overhead v3p3 sys - v2p5 i load = 5 ma, reduce v3p3d until v2p5 drops 200 mv 440 mv 6.4.9 c rystal o scillator measurement conditions: crystal disconnected, test load of 200 pf/100 k between xout and gndd. table 88 : crystal oscillator performance specifications p arameter condition m in t yp max unit maximum output power to crystal crystal connected , see note 1 1 w xin to xout capacitance (see note 1) 3 pf capacitance change on xout rtca _adj = 7f to 0, bias voltage = unbiased vpp = 0.1 v 15 pf note: 1. guaranteed by design; not production tested. downloaded from: http:///
71m6545/71M6545H data sheet v2 119 6.4.10 phase - locked loop ( pll) table 89 : pll performance specifications parameter condition min typ max unit pll power - up settling time pll_fast =0, v3p3 = 0 to 3.3 v step measured from first edge of mck (tmux2out pin) 3 ms pll_fast settling time pll_fast rise pll_fast fall v3p3=0 3 3 ms ms pll slp to msn settling time pll_fast =0 3 ms downloaded from: http:///
71m6545/71M6545H data sheet 120 v2 6.4.11 71m6545/h vref table 90 shows the performance specifications for the 71m6545/h adc reference voltage ( vref ) . table 90 : 71m6545/h vref performance specifications p arameter condition m in t yp max unit vref output voltage, vref(22 ) t a = 22 oc 1.193 1.195 1.197 v vref output voltage, vref(22 ) pll_fast =0 1.195 v vref chop step , trimmed vref(chop=01) ? vref(chop=10) - 10 10 mv vref power supply sensitivity vref / v3p3a v3p3a = 3.0 to 3.6 v - 1.5 1.5 mv/v vref input impedance vref_dis = 1 , vref = 1.3 v to 1.7 v 100 k vref output impedance vref_c al = 1, i load = 10 a, - 10 a 3.2 k vnom definition (see note 2 ) 2 )22 ( 1 )22 ( )22( )( 2 tc t tc t vref t vnom ? + ? + = v if temperature characterization trim information is available (71m654 5h) vnom temperature coefficients : tc1 = tc2 = 35.091+0.01764 ?trimt +1.587 ? ( trimbgb ? trimbgd ) ? 0. 557 ? 2.8 ? 10 ?4 ? ????? v/c v/c 2 vref(t) deviation from vnom(t) (see note 1): 62 10 )( )( )( 6 t vnom t vnom t vref ? - 10 +10 ppm /c if temperature characterization trim information is not available (71M6545H ) vnom temperature coefficients : tc1 = tc2 = trimt ? ? 95.4 275 trimt ? ? ? 00028 .0 557 .0 v/c v /c 2 vref(t) deviation from vnom(t) (see note 1): 62 10 )( )( )( 6 t vnom t vnom t vref ? - 40 +40 ppm /c vref aging 25 ppm / year notes: 1. guaranteed by design; not production tested. 2. this relationship describes the nominal behavior of vref at different temperatur es, as governed by a second order polynomial of 1 st and 2 nd order coefficients tc1 and tc2. 3. for the parameters in this table, u nless otherwise specified, vref_dis = 0 , pll_fast =1 downloaded from: http:///
71m6545/71M6545H data sheet v2 121 6.4.12 adc converter ( 71m6545/h ) table 91 : adc converter performance specifications p arameter condition m in t yp max unit recommended input range (vin - v3p3a ) - 250 250 mv peak voltage to current crosstalk ) cos( * 10 6 vcrosstalk vin vin vcrosstalk ? (see note 1) vin = 200 mv peak, 65 hz, on vadc8 (va) or vadc9 (vb) or vadc10 (vc). vcrosstalk = largest mea surement on iadc0 - 1 or iadc2 - 3 or iadc4 - 5 or iadc6 -7 - 10 10 v/v input impedance, no pre - amp vin= 65 hz 40 90 k a dc gain error vs %power supply variation 3.3/3 3 100 / 357 10 6 a p v v nv nout in pk ? ? vin=200 mv pk, 65 hz v3p3a=3.0 v, 3.6 v 50 ppm / % input offset iadc0=iadc1=v3p3a iadc0=v3p3a diff0_e =1, pre_e =0 diff0_e =0 , pre_e =0 - 10 - 10 10 10 mv mv thd @ 250mvpk name fir_len adc_div pll_fast mux_div a 0 0 0 3 b 1 0 0 2 c 0 0 1 11 d 1 0 1 6 e 2 0 1 4 f 0 1 0 2 g 0 1 1 6 h 1 1 1 3 j 2 1 1 2 v in = 65hz, 250mvpk, 64kpts fft, blackman harris window. a b - 82 c d - 84 e f - 83 g h - 86 j a - 75 b - 75 c - 75 d - 75 e - 75 f - 75 g - 75 h - 75 j - 75 db thd @ 20mvpk name fir_len adc_div pll_fast mux_div a 0 0 0 3 b 1 0 0 2 c 0 0 1 11 d 1 0 1 6 e 2 0 1 4 f 0 1 0 2 g 0 1 1 6 h 1 1 1 3 j 2 1 1 2 v in = 65hz, 20mvpk, 64kpts fft, blackman harris window. a - 85 b - 91 c - 85 d - 91 e - 93 f - 85 g - 85 h - 91 j - 93 db lsb size : name fir_len adc_div pll_fast mux_div a 0 0 0 3 b 1 0 0 2 c 0 0 1 11 d 1 0 1 6 e 2 0 1 4 f 0 1 0 2 g 0 1 1 6 h 1 1 1 3 j 2 1 1 2 vin=65hz, 20mvpk, 64kpts fft, blackman - harris window a 3470 b 406 c 3040 d 357 e 151 f 3470 g 3040 h 357 j 151 nv digital full - scale: name fir_len adc_div pll_fast mux_div a 0 0 0 3 b 1 0 0 2 c 0 0 1 11 d 1 0 1 6 e 2 0 1 4 f 0 1 0 2 g 0 1 1 6 h 1 1 1 3 j 2 1 1 2 a: 91125 b: 778688 c: 103823 d: 884736 e: 2097152 f: 91125 g: 103823 h: 884736 j: 2097152 lsb downloaded from: http:///
71m6545/71M6545H data sheet 122 v2 note: 1. guaranteed by design; not production tested. 2. unless stated otherwise, the following test conditions apply to all the par ameters provided in this table: fir_len[1:0] =1, vref_dis =0, pll_fast =1, adc_div =0, mux_div =6, lsb values do not include the 9 - bit left shift at ce input. 6.4.13 pre - amplifier for iadc0 - iadc1 table 92 : pre - amplifier performance specifications parameter condition min typ max unit differential gain vin=30mv differential vin=15mv differential (see note 1) t a = 5 ? c, v3p3=3.3 v, pre_e =1, fir_len =2, diff0 _e =1, 2520hz sample rate 7.8 7.8 7.92 7.92 8.0 8.0 v/v v/v gain variation vs v3p3 vin=30mv differential (see note 1) v3p3 = 2.97 v, 3.63 v - 100 100 ppm/% gain variation vs temp vin=30mv differential (see note 1) t a = - 40 ? c, 85 ? c 10 - 25 - 80 ppm/c phase shift, vin=30mv differential (see note 1) t a = 25 ? c, v3p3=3.3 v -6 6 mo preamp input current iadc0 iadc1 pre_e =1, fir_len =10, diff0_e =1 2520hz sample rate, iadc0=iadc1=v3p3 4 4 9 9 16 16 ua ua preamp+adc thd vin=30mv differential vin=15mv differential t a = 25 ? c, v3p3=3.3 v , pre_e =1, fir_len =2 , diff0 _e =1, 2520hz sample rate. - 82 - 86 db db preamp offset iadc0=iadc1=v3p3+30mv iadc0=iadc1= v3p3+15mv iadc0=iadc1= v3p3 iadc0=iadc1= v3p3 - 15mv iadc0=iadc1= v3p3 - 30mv t a = 25 ? c, v3p3=3.3 v, pre_e =1, fir_len =10, diff0 _e =1, 2520hz sample rate - 0.63 - 0.57 - 0.56 - 0.56 - 0.55 mv mv mv mv mv note: 1. guaranteed by design; not production tested. downloaded from: http:///
71m6545/71M6545H data sheet v2 123 6.5 t iming s pecifications 6.5.1 flash memory table 93 : flash memory timing specifications p arameter condition m in t yp max unit flash write cycles - 40 c to +85 c 20,000 cycles flash data retention 25 c 85 c 100 10 years flash byte writes between page or mass erase operations 2 cycles write time per byte 21 s page erase (1024 bytes) 21 ms mass erase 21 ms 6.5.2 spi slave table 94 . spi slave timing specifications parameter condition min typ max unit spi setup time spi_di to spi_ck rise 10 ns spi hold time spi_ck rise to spi_di 10 ns spi output delay spi_ck fall to spi_d0 40 ns spi recovery time spi_csz fall to spi_ck 10 ns spi removal time spi_ck to spi_csz rise 15 ns spi clock high 40 ns spi clock low 40 ns spi clock freq spi freq/mpu freq 2.0 mhz/mhz spi transaction space spi_csz rise to spi_csz fall 4.5 mpu cycles 6.5.3 eeprom i nterface table 95 : eeprom interface timing p arameter condition m in t yp max unit write clock frequency (i 2 c) ckmpu = 4.9 mhz, using interrupts 310 khz ckmpu = 4.9 mhz, bit - banging dio2/3 pll_fast = 0 10 0 khz write clock frequency (3 - wire) ckmpu = 4.9 mhz pll_fast = 0 pll_fast = 1 160 500 khz downloaded from: http:///
71m6545/71M6545H data sheet 124 v2 6.5.4 reset pin table 96 : reset pin timing p arameter condition m in t yp max unit reset pulse width 5 s reset pulse fall time (see note 1) 1 s note: 1. guaranteed by design; not production tested. 6.5.5 r eal - time clock (rtc) table 97 : rtc range for date p arameter condition m in t yp max unit range for date 2000 ? 2255 year downloaded from: http:///
71m6545/71M6545H data sheet v2 125 6.6 64 - pin lqfp p ackage outline drawing controlling dimensions are in mm. 11.7 12.3 0.60 typ. 1.40 1.60 11.7 12.3 0.00 0.20 9.8 10.2 0.50 typ. 0.14 0.28 pin no. 1 indicator + figure 37 : 64 - pin lqfp package outline downloaded from: http:///
71m6545/71M6545H data sheet 126 v2 6.7 71m6545/h pinout 1 71m6545/h 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 32 26 27 28 29 30 17 18 19 20 21 22 23 24 25 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 6463 62 61 51 52 53 54 55 56 57 58 59 6049 50 spi_di spi_csz v3p3d dio29dio28 vdd dio25 spi_do tx dio24 dio23dio22 dio21 dio20 dio19 dio1 /vpulse dio3 /sdata dio55 dio14dio13 dio10 dio11 dio12 dio9 dio8/ di dio7/ ypulse dio6/ xpulse dio5dio4 dio2 /sdck dio0 /wpulse v3p3sys xin ice_e vbat_rtc e_rxtxe_tclk e_rst rx tmuxoutv3p3a gnda vadc8 (va) pbnc test xout iadc0iadc1 reset tmux2out spi_cki vref iadc2iadc3 gndd gndd gnda vadc9 (vb)vadc10 (vc) iadc7 iadc6 iadc4iadc5 10/7/2010 figure 38 : pinout for the l qf p- 64 package downloaded from: http:///
71m6545/71M6545H data sheet v2 127 6.8 71m6545/h pin d escriptions 6.8.1 71m6545/h power and ground pins table 98 lists the power and ground pins. pin types: p = power, o = output. the circuit number denotes the equivalent circuit, as specified under 6.8.4 . table 98 : 71m6545/h power and ground pins pin no. name type circuit description 47, 50 gnda p C analog ground: this pin should be connected directly to the ground plane. 16, 38 gndd p C digital ground: this pin is connected directly to the ground plane. 55 v3p3a p C analog power supply: a 3.3 v power supply is connected to this pin. v3p3a must be the same voltage as v3p3sys. 45 v3p3sys p C system 3.3 v supply. this pin is connected to a 3.3 v power supply. 5 v3p3d o 13 auxiliary voltage output of the chip. in mission mode, this pin is con nected to v3p3sys by the internal selection switch. a bypass capacitor to ground must not exceed 0.1 f. 4 vdd o 10 the output of the 2.5v regulator. this pin is powered in msn mode. a 0.1 f bypass capacitor to ground must be connected to this pin. 46 vbat_rtc p 12 rtc and oscillator power supply. a battery may be optionally connected between vbat_rtc and gndd. if no battery is used, connect vbat_rtc to v3p3sys. downloaded from: http:///
71m6545/71M6545H data sheet 128 v2 6.8.2 71m6545/h analog pins table 99 lists the analog pins. pin types: o = output, i = input. the circuit num ber denotes the equivalent circuit, as specified in 6.8.4 . table 99 : 71m6545/h analog pins pin no. name type circuit description 57 56 44 43 42 41 40 39 iadc0 iadc1 iadc2 iadc3 iadc4 iadc5 iadc6 iadc7 i 6 differential or single - ended analog line current sense inputs: these pins are voltage inputs to the internal a/d converter. typically, they are connected to the outputs of current sensors. unused pins must be tied to v3p3a . when configured as differential inputs (i.e., by setting the diffx_e control bits, where x=0, 2, 4, 6), p in s are paired to form differential inputs pairs: iadc0 - iadc1, i adc2 -i adc3 , i adc4 - i adc5 , and iadc6 - iadc7. iadc2 - iadc3, iadc4 - iadc5 and iadc6 - iadc7 may be configured for communication with the 71m6xx3 remote isolated sensor interface (i.e., by setting the rmtx_e control bits, where x=2, 4, 6). when configured as remote sensor interfaces, these pins form balanced digital pairs for bi - directional digital communications with a 71m6xx3 remote isolated sensor. 54 53 52 vadc8 (va) vadc9 (vb ) vadc10 ( vc ) i 6 line voltage sense inputs: these pins are voltage inputs to the internal a/d converter. typically, they are connected to the outputs of resistor dividers. unused pins must be tied to v3p3a. 58 vref o 9 voltage reference for the adc. this pin must be left unconnected (floating). the vref pin must be kept turned off for normal operation (see vref_cal , i/o ram 0x2704[7] ). 48 49 xin xout i o 8 crystal inputs: a 32 khz crystal should be connected across these pins. typically, a 15 pf capacitor is also connected from xin to gnda and a 10 pf capacitor is connected from xout to gnda. it is important to minimize the capacitance between these pins. see th e crystal manufacturer datasheet for details. if an external clock is used, a 150 mv (p - p) clock signal should be applied to xin, and xout should be left unconnected. downloaded from: http:///
71m6545/71M6545H data sheet v2 129 6.8.3 71m6545/h digital pins table 100 lists the digital pins. pin types: o = output, i = input, i/o = input /output, n/c = no connect. the circuit number denotes the equivalent circuit, as specified in 6.8.4 . table 100 : 71m6545/h digital pins pin no. name type circuit description 31 dio0/wpulse i/o 3, 4 multiple - use pins. c onfigurable as dio or its alternate function . alternat e functions with proper selection of associated i/o ram registers are: dio0 = wpulse ( 31 ) dio1 = vpulse (30 ) dio2 = sdck ( 29 ) dio3 = sdata ( 28 ) dio6 = xpulse ( 25 ) dio7 = ypulse ( 24 ) dio8 = di ( 23 ) unused pins must be configured as outputs or terminated to v3p3/gndd. 30 dio1/vpulse 29 dio2/sdck 28 dio3/sdata 27 dio4 26 dio5 25 dio6/xpulse 24 dio7/ypulse 23 dio8/di 17 C 22 dio[ 14 :9] 8C14 dio[ 25 : 19 ] 6C7 dio[2 9: 28 ] 32 dio 55 3 2 1 64 spi_csz spi_do spi_di spi_cki i o i i 3, 4 spi interface pins. 36 34 35 e_rxtx e_rst e_tclk i/ o i/o o 1, 4 4 e mulator port pins. these pins are activated when the ice_e pin is pulled high . 37 ice_e i 2 ice enable. for production units, this pin should be pulled to gnd to disable the emulator port. 62 63 tmuxout tmux2out o 4 multiplexer/clock output pins . 61 reset i 2 chip reset: this input pin is used to reset the chip into a known state. for normal operation, this pin is pulled low. to reset the chip, this pin is pulled high. this pin has an internal 30 a (nominal) current source pull - down. no external reset circ uitry is necessary. 33 rx i 3 uart0 input. if this pin is unused it must be terminated to v3p3d or gndd. 15 tx o 4 uart 0 output. 51 test i 7 enables production test. this pin must be grounded in normal operation. 60 pb i 3 push button input. this pin must be at gndd when not active or unused. pb does not have an internal pull - up or pull - down resistor . 59 nc n/c -- do not connect this pin . downloaded from: http:///
71m6545/71M6545H data sheet 130 v2 6.8.4 i/o equivalent circuits oscillator equivalent circuit type 8: oscillator i/o digital input equivalent circuit type 1: standard digital input or pin configured as dio input with internal pull-up gnd d 110k v3p3d cmos input v3p3d digital input pin digital input type 2: pin configured as dio input with internal pull-down gnd d 110k gnd d cmos input v3p3d digital input pin digital input type 3: standard digital input or pin configured as dio input gnd d cmos input v3p3d digital input pin cmos output gnd d v3p3d gnd d v3p3d digital output equivalent circuit type 4: standard digital output or pin configured as dio output digital output pin to mux gnda v3p3a analog input equivalent circuit type 6 : adc input analog input pin comparator input equivalent circuit type 7: comparator input gnda v3p3a to comparator comparator input pin to oscillator gndd v3p3d oscillator pin vref equivalent circuit type 9: vref from internal reference gnda v3p3a vref pin v2p5 equivalent circuit type 10: v2p5 from internal reference gnd d v3p3d v2p5 pin vbat_rtc equivalent circuit type 12: vbat_rtc power gndd power down circuits vbat_rtc pin v3p3d equivalent circuit type 13: v3p3d from v3p3sys v3p3d pin 10 figure 39 : i/o equivalent circuits downloaded from: http:///
71m6545/71M6545H data sheet v2 131 7 o rdering i nformation 7.1 71m6545/h ordering guide r efer to the 71m6xxx data sheet for the 71m6xx3 ordering guide information. table 101 . 71m6545/h ordering guide part part description (package, typical accuracy) flash (kb)/ ram (kb) size packaging order number package marking 71m6545 64 lqfp lead (pb) - free, 0. 1% 32/3 bulk 71m6545 - igt/f 71m6545 - igt 71m6545 64 lqfp lead (pb) - free, 0. 1% 32/3 tape a nd reel 71m6545 - igtr/f 71m6545 - igt 71M6545H * 64 lqfp lead (pb) - free, 0.1% 64/5 bulk 71m6545 h- igt/f 71m6545 h- igt 71m6545 h* 64 lqfp lead (pb) - free, 0.1% 64/5 tape a nd reel 71m6545 h- igtr/f 71m6545 h- igt * future productcontact factory for availability. 8 related information the following documents related to the 71m6545/h and 71m6xx3 are available : ? 71m6545/h data sheet ( this document) ? 71m6xxx data sheet ? 71m654 x software users guide (sug) 9 contact information for technical support or more information about maxim products , contact technical support at www.maximintegrated.com/support . downloaded from: http:///
71m6545/71M6545H data sheet 132 v2 a ppendix a: acronyms afe analog front end amr automatic meter reading ansi american national standards institute ce compute engine dio digital i /o dsp digital signal processor fir finite impulse response i 2 c inter - ic bus ice in - circuit emulator iec international electrotechnical commission mpu microprocessor unit (cpu) pll phase - locked loop rms root mean square sfr special function register spi serial peripheral interface tou time of use uart universal asynchronous receiver/transmitter downloaded from: http:///
71m6545/71M6545H data sheet maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves t he right to change the circuitry and specifications withou t notice at any time. the parametric values (min and max limits) shown in the electrical chara cteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2013 maxim integrated products maxim integrated and the maxim integrated logo are trademarks of maxim i ntegrated products, inc. appendix b : revision hi story revision number revision date description pages changed 1.0 4/11 initial release 2 10/13 replaced figure 12, u pdat ed pls_inv description on t able 61, updated document footers, added warning note on spi flash mode section, updated ien0 bit function and external mpu interrupts table, changed ceconfig bit 23 to reserved, corrected spi slave port diagram (figure 20), updated the text description of the signal input pins section, combined columns 3 and 4 of table 32, updated the interrupt structure diagram, updated the required ce code and settings notes about mux_div[3:0], added a note about v_ang_cnt under table 74 all downloaded from: http:///

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